TITLE

Advanced lift-off planarization process for Josephson integrated circuits

AUTHOR(S)
Ishida, Ichiro; Tahara, Syuichi; Wada, Yoshifusa
PUB. DATE
July 1988
SOURCE
Applied Physics Letters;7/25/1988, Vol. 53 Issue 4, p316
SOURCE TYPE
Academic Journal
DOC. TYPE
Article
ABSTRACT
An advanced lift-off planarization process utilizing an undercut technique of a photoresist etching mask has been developed to achieve planarization of thin-sputtered and fine-patterned films that are necessary for high-performance Josephson integrated circuits (IC’s). A stack of the same kind of photoresist layers, including the modified layer between them, has been utilized as an etching mask providing fine-patterned film profiles with minimized resist degradation by the top photoresist protection layer. This advanced planarization process brings about smooth surfaces having no residues and no grooves along pattern edges. 30 nm deviation from planarity has been demonstrated on a 200-nm-thick planarized Nb superconducting layer. A four-level interconnection of Josephson IC’s was successfully fabricated by this process.
ACCESSION #
9827509

 

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