In situ observation of lamp zone melting of Si films on patterned SiO2

Dutartre, D.
February 1986
Applied Physics Letters;2/3/1986, Vol. 48 Issue 5, p350
Academic Journal
Using video recording equipment we are able to visualize and study both the melting and freezing interfaces in lamp zone melting recrystallization of silicon on insulator (SOI) films. A so-called ‘‘explosive’’ melting has been observed, corresponding to a noncontinuous advance of the front. We also show the effectiveness of an etched pattern in the underlying SiO2 on the modulation of the solidification front. We thereby confirm the entrainment effect of this pattern. We observe then the effect of the scan speed on the liquid/solid interface morphology together with the entrainment efficiency.


Related Articles

  • Enhancement of phosphorus activation in vacancy engineered thin silicon-on-insulator substrates. Smith, A. J.; Gwilliam, R. M.; Stolojan, V.; Knights, A. P.; Coleman, P. G.; Kallis, A.; Yeong, S. H. // Journal of Applied Physics;Nov2009, Vol. 106 Issue 10, p103514-1 

    The concentration of vacancy-type defects in a silicon-on-insulator substrate consisting of a 110 nm silicon overlayer and a 200 nm buried oxide has been quantified using variable energy positron annihilation spectroscopy following 300 keV Si+ ion implantation to a dose of 1.5×1015 cm-2 and...

  • Cavity-enhanced photoluminescence of SiGe/Si multiquantum wells grown on silicon-on-insulator substrate. Li, C.B.; Huang, C.J.; Cheng, B.W.; Zuo, Y.H.; Mao, R.W.; Luo, L.P.; Yu, J.Z.; Wang, Q.M. // Journal of Applied Physics;5/15/2004, Vol. 95 Issue 10, p5914 

    Sharp and strong room-temperature photoluminescence (PL) of the Si 0.59 Ge 0.41/Si multiquantum wells grown on the silicon-on-insulator substrate is investigated. The cavity formed by the mirrors at the surface and the buried SiO 2 interface enhances the PL emission and has a...

  • Determination of oxide fixed charge at the top and bottom Si/SiO[sub 2] interfaces of.... Arnold, Emil // Applied Physics Letters;5/29/1995, Vol. 66 Issue 22, p3027 

    Characterizes the silicon-on-insulator (SOI) allowing separate determination of oxide fixed charges at silicon (Si)/Si dioxide interfaces. Use of the depletion-type metal oxide semiconductor in characterizing thin SOI devices; Information on bias voltage determinants; Determination of oxide...

  • Optimal preamorphization conditions for the formation of highly activated ultra shallow junctions in Silicon-On-Insulator. Hamilton, J. J.; Collart, E. J. H.; Bersani, M.; Giubertoni, D.; Gennaro, S.; Bennett, N. S.; Cowern, N. E. B.; Kirkby, K. J. // AIP Conference Proceedings;2006, Vol. 866 Issue 1, p73 

    Preamorphising implants (PAI) in Silicon-on-insulator (SOI) compared with bulk silicon substrates have been shown to improve junction properties. This paper studies the optimization of electrical behavior of this process in SOI. We will show that the deactivation caused by end-of-range (EOR)...

  • Transistor needle chip for recording in brain tissue. Felderer, Florian; Fromherz, Peter // Applied Physics A: Materials Science & Processing;Jul2011, Vol. 104 Issue 1, p1 

    We report on a proof-of-principle experiment for the direct interfacing of transistors with intact brain tissue. A transistor needle chip (TNC) with a TiO surface is fabricated from a silicon-on-insulator wafer and impaled into an acute brain slice cut from hippocampus of the rat. While...

  • Interface trap density evaluation on bare silicon-on-insulator wafers using the quasi-static capacitance technique. Pirro, L.; Ionica, I.; Ghibaudo, G.; Mescot, X.; Faraone, L.; Cristoloveanu, S. // Journal of Applied Physics;5/7/2016, Vol. 119 Issue 17, p1 

    This paper presents a detailed investigation of the quasi-static capacitance-voltage (QSCV) technique in pseudo-metal-oxide-semiconductor field effect transistor (pseudo-MOSFET) configuration for evaluating the interface quality of bare silicon-on-insulator (SOI) wafers, without processing...

  • Behavior of Charge in a Buried Insulator of Silicon-on-Insulator Structures Subjected to Electric Fields. Nikolaev, D. V.; Antonova, I. V.; Naumova, O. V.; Popov, V. P.; Smagulova, S. A. // Semiconductors;Jul2002, Vol. 36 Issue 7, p800 

    The behavior of charge in a buried oxide of the silicon-on-insulator structures obtained using the Dele-Cut technology was studied by keeping the structures under a voltage with an electric-field strength of 2-5.5 MV/cm. A mobile positive charge drifting under the effect of applied voltage was...

  • Transformation of Interface States in Silicon-on-Insulator Structures under Annealing in Hydrogen Atmosphere. Antonova, I. V.; Stano, I.; Nikolaev, D. V.; Naumova, O. V.; Popov, V. P.; Skuratov, V. A. // Semiconductors;Jan2002, Vol. 36 Issue 1, p60 

    Changes induced by annealing the spectrum of states on a Si/SiO[sub 2] interface obtained by direct bonding and on a Si(substrate)/〈thermal SiO[sub 2]〉 interface in silicon-on-insulator (SOI) structures were investigated by charge-related deep-level transient spectroscopy. The...

  • Transistor Elements for 30nm Physical Gate Lengths and Beyond. Doyle, Brian; Arghavani, Reza; Barlage, Doug; Datta, Suman; Doczy, Mark; Kavalieros, Jack; Murthy, Anand; Chau, Robert // Intel Technology Journal;5/16/2002, Vol. 6 Issue 2, p42 

    We have fabricated conventional planar transistors of various gate lengths down to as small as 10nm polysilicon gate lengths, in order to examine transistor scaling. At 30nm gate lengths, the devices show excellent device characteristics, indicating that this node can be met with conventional...


Read the Article


Sorry, but this item is not currently available from your library.

Try another library?
Sign out of this library

Other Topics