TITLE

Comparative Survey of Various Low Power Clock Gating Techniques for ALU Design

AUTHOR(S)
Raja, L.; Thanushkodi, K.
PUB. DATE
July 2014
SOURCE
Australian Journal of Basic & Applied Sciences;Jul2014, Vol. 8 Issue 10, p231
SOURCE TYPE
Academic Journal
DOC. TYPE
Article
ABSTRACT
Background: At present scenario, the frequent and the most fundamental component in low power processor design is Arithmetic and Logic Unit (ALU). Further Power utilization due to clock gated ALU can be noteworthy in high performance systems. In general functionality of the ALU's is a mixture of arithmetic and logic operations which are realized by means of combinational circuits. In attendance to two high-speed and low-power ALU cells designed with an unconventional internal logic structure, CMOS bootstrapped dynamic logic, latch free, latch based and pass-transistor logic styles that lead to have a reduced power-delay product (PDP) and total power utilization. Objective: This paper deals with the design of ALU Clock Gating circuits then its Low Power Arithmetic and Logic Unit that has been developed as part of low power processor design. Results: The comparison among all the ALU and its clocking circuits are reported as having a low PDP, in stipulations of power delay product and power consumption. The proposed logic style improves switching speed by boosting the gate source voltage of transistors along timing-critical signal paths. Conclusion: The proposed method outperforms the conventional counterparts in terms of power consumption and PDF. This style helps to minimizes power operating cost by allowing a single boosting circuit to be shared by complementary outputs. Post-layout simulations show that the proposed ALU's outperform existing counterparts.
ACCESSION #
97368484

 

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