TITLE

FPGA-Based Implementation of Text Analyser and Syllable Preparation for Concatenative Speech Synthesis of Tamil Language

AUTHOR(S)
Jayasankar, T.; Vijayaselvi, J. Arputha
PUB. DATE
July 2014
SOURCE
Australian Journal of Basic & Applied Sciences;Jul2014, Vol. 8 Issue 10, p102
SOURCE TYPE
Academic Journal
DOC. TYPE
Article
ABSTRACT
This paper describes about the design and development of an FPGA based Text Analysis and syllable preparation for Concatenation Text to Speech Synthesis (CTTS) of Tamil Language. Research on TTS conversion is a large enterprise that shows an impressive improvement in the last couple of decades. A complete implementation of CTTS is composed of Text analysis, prosody control, and speech synthesis. A text analysis is the TTS front end deals with converting text in to pronunciation form, called Text Normalization and get the prosodic information that may be obtainable by analysing various underlying structures of the text. The texts are converted to the pronunciation form using text analysis module in natural speech synthesis system. Then development of CTTS is carried out by addressing the text analysis issues include text normalization, numerical words, abbreviation and syllable segmentation w The implementation of this system will be tested using Xilinx FPGA VIRTEX V Board. This hardware implementation through FPGA makes the text analyser eases the integration of any other embedded devices for TTS.
ACCESSION #
97368467

 

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