TITLE

Static and dynamic task mapping onto network on chip multiprocessors

AUTHOR(S)
Bolaños-Martínez, Freddy; Edison Aedo, José; Rivera-Vélez, Fredy
PUB. DATE
June 2014
SOURCE
Dyna;Jun2014, Vol. 81 Issue 185, p28
SOURCE TYPE
Academic Journal
DOC. TYPE
Article
ABSTRACT
Due to its scalability and flexibility, Network-on-Chip (NoC) is a growing and promising communication paradigm for Multiprocessor System-on-Chip (MPSoC) design. As the manufacturing process scales down to the deep submicron domain and the complexity of the system increases, fault-tolerant design strategies are gaining increased relevance. This paper exhibits the use of a Population-Based Incremental Learning (PBIL) algorithm aimed at finding the best mapping solutions at design time, as well as to finding the optimal remapping solution, in presence of single-node failures on the NoC. The optimization objectives in both cases are the application completion time and the network's peak bandwidth. A deterministic XY routing algorithm was used in order to simulate the traffic conditions in the network which has a 2D mesh topology. Obtained results are promising. The proposed algorithm exhibits a better performance, when compared with other reported approaches, as the problem size increases.
ACCESSION #
97250680

 

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