Analysis of C-face 4H-SiC MOS capacitors with ZrO2 gate dielectric

Le-Shan Chan; Yu-Hao Chang; Kung-Yen Lee
March 2014
Materials Science Forum;2014, Vol. 778-780, p635
Academic Journal
ZrO2 films were deposited on C-face 4H-SiC substrates by using an RF sputter at a temperature of 200°C. Then, ZrO2 films were treated with RTA (rapid thermal annealing) process in Argon (Ar) and N2 ambient at 600°C, 700°C and 800°C for 4 minutes, respectively. The samples with RTA process show the lower leakage currents. As the measurement temperature increases from room temperature (RT) to 150°C, the dielectric breakdown field reduces from 0.53 MV/cm to 0.41 MV/cm. The C-V curves shift to the left side as the measurement temperature increases from RT to 150°C. It also shows the existence of interface states at the deep level observed from the interface state ledge on C-V curves of capacitors at elevated measurement temperature.


Related Articles

  • N2O-grown oxides/4H-SiC (0001), (0338), and (1120) interface properties characterized by using p-type gate-controlled diodes. Noborio, Masato; Suda, Jun; Kimoto, Tsunenobu // Applied Physics Letters;11/10/2008, Vol. 93 Issue 19, p193510 

    The N2O-grown SiO2/4H-SiC (0001), (0338), and (1120) interface properties in p-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) have been characterized by using gate-controlled diodes. Although the inversion layer is not formed in...

  • Influence of Diverse Post-Trench Processes on the Electrical Performance of 4H-SiC MOS Structures. Banzhaf, C. T.; Grieb, M.; Trautmann, A.; Bauer, A. J.; Frey, L. // Materials Science Forum;2014, Vol. 778-780, p595 

    This paper focuses on the evaluation of subsequent process steps (post-trench processes, PTPs) after 4H silicon carbide (4H-SiC) trench etching with respect to the electrical performance of trenched gate metal oxide semiconductor field effect transistors (Trench-MOSFETs). Two different types of...

  • Step-Bunching Dependence of the Lifetime of MOS Capacitors on 4° Off-Axis Si-Face 4H-SiC Epitaxial Wafers. Akira Bandoh; Kenji Suzuki; Yoshihiko Miyasaka; Hiroshi Osawa; Takayuki Sato // Materials Science Forum;2014, Vol. 778-780, p611 

    The step-bunching dependence of the lifetime of metal-oxide-semiconductor capacitors on 4° off-axis 4H-SiC epitaxial wafers was investigated. The effects of the C/Si ratios in epitaxial growth and the substrate properties were examined. Step-bunching was observed at the base of triangle or...

  • High Mobility 4H-SiC MOSFETs Using Lanthanum Silicate Interface Engineering and ALD Deposited SiO2. Xiangyu Yang; Bongmook Lee; Misra, Veena // Materials Science Forum;2014, Vol. 778-780, p557 

    In this work, we have developed a novel gate stack to enhance the mobility of Si face (0001) 4H-SiC lateral MOSFETs while maintaining a high threshold voltage. The gate dielectric consists a thin lanthanum silicate layer at SiO2 dielectric interface and SiO2 deposited by atomic layer deposition....

  • Electronic structure and band alignment at the HfO2/4H-SiC interface. Tanner, Carey M.; Choi, Jongwoo; Chang, Jane P. // Journal of Applied Physics;2/1/2007, Vol. 101 Issue 3, p034108 

    To evaluate the potential of HfO2 as a gate dielectric in SiC power metal-oxide-semiconductor field effect transistors (MOSFETs), the band alignment at the HfO2/4H-SiC interface was determined by x-ray photoelectron spectroscopy (XPS) measurements and first-principles calculations using density...

  • On the Evaluation of Gate Dielectrics for 4H-SiC Based Power MOSFETs. Nawaz, Muhammad // Active & Passive Electronic Components;1/1/2015, Vol. 2015, p1 

    This work deals with the assessment of gate dielectric for 4H-SiC MOSFETs using technology based two-dimensional numerical computer simulations. Results are studied for variety of gate dielectric candidates with varying thicknesses using well-known Fowler-Nordheim tunneling model. Compared to...

  • Simple method for the fabrication of a high dielectric constant metal-oxide-semiconductor capacitor embedded with Pt nanoparticles. Sargentis, Ch.; Giannakopoulos, K.; Travlos, A.; Boukos, N.; Tsamakis, D. // Applied Physics Letters;2/13/2006, Vol. 88 Issue 7, p073106 

    We present a simple method for the fabrication of Pt nanoparticles embedded in a high-k dielectric. The nanoparticles are formed during the first deposition stages of a thin Pt layer on a 30 Ã… SiO2 tunneling layer, at room temperature, performed with electron-beam (e-beam) evaporation of...

  • Effects of the growth rate on the quality of 4H silicon carbide films for MOSFET applications. Camarda, M.; Privitera, S.; Anzalone, R.; Piluso, N.; Fiorenza, P.; Alberti, A.; Pellegrino, G.; La Magna, A.; La Via, F.; Vecchio, C.; Mauceri, M.; Litrico, G.; Pecora, A.; Crippa, D. // Materials Science Forum;2014, Vol. 778-780, p95 

    In this paper we investigate the role of the growth rate (varied by changing the Si/H2 ratio and using TCS to avoid Si droplet formation) on the surface roughness (Rq), the density of single Shockley stacking faults (SSSF) and 3C-inclusions (i.e. epi-stacking faults, ESF). We find that optimized...

  • 4H-SiC MOS Capacitors and MOSFET Fabrication with Gate Oxidation at 1400°C. Naik, Harsh; Chow, T. Paul // Materials Science Forum;2014, Vol. 778-780, p607 

    This paper compares the performance of 4H-SiC MOS capacitors and MOSFETs made using the conventional NO annealing process and a high-temperature (1400° C) dry oxidation process. Through extensive C-V, G-ω, I-V and Hall measurements, the limitations of both the processes are discussed.


Read the Article


Sorry, but this item is not currently available from your library.

Try another library?
Sign out of this library

Other Topics