TITLE

Design and Analysis of Reduced Test Power in Scan Based Design

AUTHOR(S)
Sowmiya, G.; Saravanan, S.; Vijaysai, R.
PUB. DATE
April 2013
SOURCE
International Journal of Engineering & Technology (0975-4024);Apr/May2013, Vol. 5 Issue 2, p692
SOURCE TYPE
Academic Journal
DOC. TYPE
Article
ABSTRACT
Low power VLSI testing is indispensible in switching components and number of hardware/software-based techniques has been still developed to minimize the dynamic power dissipation. In earlier days, primary concerns of VLSI design were focused in area, performance, cost and reliability. But in current years, the design constraints have begun to change because of increasing low power testing. XOR network based techniques have been widely implemented for large scan chain design owing to its high compression ratio. The proposed work explores the reduction of scan power by reducing the number of switching in the XOR network. This work is also associated with Travelling Salesman problem to find out the least number of switching.
ACCESSION #
93342334

 

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