How Long Until the Next Killer Application?
- Low-cost lithography for 300mm wafer packaging. Hermanowski, James; Cullmann, Elmar // Microlithography World;May2004, Vol. 13 Issue 2, p4
Discusses several lithographic areas for wafer-level packaging (WLP). Types of layers involved in WLP; Reasons for potential overlay inaccuracies for all wafer exposures; Key parameters affecting tool throughput related to exposure strategy.
- Clean breakthrough. Masi, Charles // Engineer (00137758);11/28/2005, Vol. 293 Issue 7689, p35
The article focuses on the new automated material handling system standard that uses front-opening universal pods (FOUPs) for cleaning semiconductor wafers. The standard mechanical interface pods are small enclosures in which wafer lots can be stored between processing steps, and transported...
- Sawing Silicon. McCabe, Peter // Advanced Packaging;Mar2005, Vol. 14 Issue 3, p26
Discusses the art and science of semiconductor wafer sawing in the U.S. Importance of experience, judgement, and high-performance equipment in the proper dicing of wafers; Wide variety of models with many options offered by silicon dicing saws; Features of diamond dicing blades; Steps involved...
- Mass Imaging Responds to Wafer-Scale Packaging Advances. Heimsch, Richard // Advanced Packaging;May2005, Vol. 14 Issue 5, p20
Reports on the application of high-accuracy mass imaging to semiconductor wafer-scale packaging. Emergence of new generations of chip-scale packages; Advances in screen printing for surface mount technology; Enhancement of paste release for wafer-level applications.
- Laser-scanning projection lithography for wafer-level packaging. Klosner, M.; Zemel, M.; Raghunandan, S.; Jain, Kanti // Microlithography World;May2004, Vol. 13 Issue 2, p11
Focuses on laser-scanning projection lithography for wafer-level packaging (WLP). Lithography requirements for WLP; Information on Anvik's HexScan laser-projection imaging system; Challenges for WLP lithographies.
- Stepper technology enabling wafer-level packaging adoption. Ranjan, Manish // Solid State Technology;Mar2008, Vol. 51 Issue 3, p35
The article reports on the adoption of wafer-level packaging (WLP) stepper technology in semiconductor assembly and test services, packaging foundries and integrated device (IC) manufacturing in the U.S. The author expresses that WLP eliminates yield loss during the lithography processing and...
- 'Chiplets' Create Multi-Species MCMs. Gurnett, Keith; Adams, Tom // Circuits Assembly;May2007, Vol. 18 Issue 5, p30
The article describes an etching and metallization process for inserting and interconnecting tiny patterned chip or chiplets into the pit in a silicon wafer. To overall objective of the approach is to build a low-cost multichip modules at the semiconductor wafer level, the authors said. An...
- Wafer-level Hermetic Cavity Packaging. Riley, George A. // Advanced Packaging;May2004, Vol. 13 Issue 5, p21
Reports on the potential cost, handling and performance advantages in packaging a wide variety of MEMS, optical and sensor devices by wafer-level hermetic cavity packaging (WLCSP). Essence of conventional WLCSP; Cost advantage of simultaneously sealing an entire wafer of cavities in vacuum;...
- A Review on Die Attach Materials for SiC-Based High-Temperature Power Devices. Chin, Hui; Cheong, Kuan; Ismail, Ahmad // Metallurgical & Materials Transactions. Part B;Aug2010, Vol. 41 Issue 4, p824
Recently, high-temperature power devices have become a popular discussion topic because of their various potential applications in the automotive, down-hole oil and gas industries for well logging, aircraft, space exploration, nuclear environments, and radars. Devices for these applications are...