TITLE

Guest Editorial: Advanced Techniques for Efficient Electronic System Design

AUTHOR(S)
Meher, Pramod; Mohanty, Saraju; Vinod, A.
PUB. DATE
December 2013
SOURCE
Circuits, Systems & Signal Processing;Dec2013, Vol. 32 Issue 6, p2539
SOURCE TYPE
Academic Journal
DOC. TYPE
Article
ABSTRACT
An introduction is presented in which the editor discusses various reports with in the issue on topics including Filter banks (FB), very large scale interrogation (VLSI), and network on Chip technology (NOC).
ACCESSION #
91716587

 

Related Articles

  • Networks-on-Chip: Architectures, Design Methodologies, and Case Studies. Sao-Jie Chen; An-Yeu Andy Wu; Jiang Xu // Journal of Electrical & Computer Engineering;2012, p1 

    An introduction is presented in which the editors discuss various papers within the issue on the Network on a Chip technology.

  • Hierarchical Agent Based NoC with DVFS Techniques. Wei Yin, Alexander; Liang Guang; Liljeberg, Pasi; Rantala, Pekka; Isoaho, Jouni; Tenhunen, Hannu // International Journal of Design, Analysis & Tools for Integrated;2011, Vol. 1 Issue 1, p32 

    Network-on-Chip (NoC) is a promising architecture in the many-core on-chip systems. A hierarchical agent based NoC architecture is proposed which enables the NoC to autonomously adjust itself, and provide maximum power efficiency, fault/variation tolerance and system flexibility. Agents are...

  • A Formal Approach to the Verification of Networks on Chip. Borrione, Dominique; Helmy, Amr; Pierre, Laurence; Schmaltz, Julien // EURASIP Journal on Embedded Systems;1/1/2009, Special section p1 

    The current technology allows the integration on a single die of complex systems-on-chip (SoCs) that are composed of manufactured blocks (IPs), interconnected through specialized networks on chip (NoCs). IPs have usually been validated by diverse techniques (simulation, test, formal...

  • Square Topology for NoCs. Ghorbanian, M.; Sabbaghi-Nadooshan, R.; Doroud, H. // Journal of Computing;Oct2011, Vol. 3 Issue 10, p43 

    In this paper different topologies are studied and their functions in networks are described. Ultimately, some novel topology are introduced and compared with existing ones in regard of factors such as power and delay. This paper proposes square topology as an efficient topology for Network on...

  • Design and Implementation of Multistage Interconnection Networks for SoC Networks. Moazez, Mahsa; Safaei, Farshad; Rezazadeh, Majid // International Journal of Computer Science, Engineering & Informa;Oct2012, Vol. 2 Issue 5, p1 

    In this paper the focus is on a family of Interconnection Networks (INs) known as Multistage Interconnection Networks (MINs). When it is exploited in Network-on-Chip (NoC) architecture designs, smaller circuit area, lower power consumption, less junctions and broader bandwidth can be achieved....

  • Comparative analysis of Scheduling Algorithms in Network On Chip using Network Calculus. Moussa, Neila; Bhar, Jamila; Nasri, Farah; Tourki, Rached // International Journal of Electrical & Computer Sciences;Jun2014, Vol. 14 Issue 3, p17 

    The design of on chip interconnection architecture (NoC) should carefully take on consideration both hardware and communication constraints in order to build up a system that meets quality of service requirements. In the NoC architecture, the on chip switch available hardware and software...

  • Implications of Electronics Technology Trends for Algorithm Design1. GREENFIELD, DANIEL; MOORE, SIMON // Computer Journal;Sep2009, Vol. 52 Issue 6, p690 

    Scaling of electronics technology has brought us to a pivotal point in the design of computational devices. Technology scaling favours transistors over wires which has led us into an era where communication takes more time and consumes more power than the computation itself. This technology...

  • Polymeric $$N$$ -stage serial-cascaded four-port optical router with scalable $$3N$$ channel wavelengths for wideband signal routing application. Luo, Qian-Qian; Zheng, Chuan-Tao; Huang, Xiao-Liang; Wang, Yi-Ding; Zhang, Da-Ming // Optical & Quantum Electronics;Jun2014, Vol. 46 Issue 6, p829 

    Device architecture and design scheme of a universal $$N$$ -stage cascaded polymer four-port optical router with scalable 3 $$N$$ channel wavelengths are proposed. Basic cross-coupling two-microring resonator routing element based on polymer materials is optimized for single-mode transmission,...

  • Investigation on an ultra-compact $$1\times 2$$ polymer electro-optic switch using cross-coupling $$2N+1$$ vertical-turning serial-coupled microrings. Luo, Qian-Qian; Zheng, Chuan-Tao; Huang, Xiao-Liang; Liang, Lei; Zhang, Da-Ming; Wang, Yi-Ding // Optical & Quantum Electronics;Sep2013, Vol. 45 Issue 9, p999 

    Generic model and thorough investigation are proposed for a novel $$1\times 2$$ polymer electro-optic (EO) switch based on one-group $$2N+1$$ vertical-turning serial-coupled microrings. For realizing boxlike flat spectrum as well as low crosstalk and insertion loss, resonance order and coupling...

Share

Read the Article

Courtesy of THE LIBRARY OF VIRGINIA

Sorry, but this item is not currently available from your library.

Try another library?
Sign out of this library

Other Topics