Computer firms take the RISC route to greater power

Chatterjee, Pratap
April 1991
New Scientist;4/27/91, Vol. 130 Issue 1766, p28
Details an agreement signed by 21 of the world's largest computer companies which may make desktop computers more powerful. The Advanced Computer Environment; Reduced instruction set computing (RISC); Agreement to model RISC chips on a single, agreed architecture; Companies which have not signed the agreement; More.


Related Articles

  • Reduced Instruction Set Computer.  // Network Dictionary;2007, p404 

    A definition of the term "reduced instruction set computer (RISC)" is presented. It refers to a type of microprocessor that recognizes a relatively limited number of instructions. RISCs can execute their instructions very fast because the instructions are so simple, RISC microprocessors require...

  • New Architecture for EIA-709.1 Protocol Implementation. Su Goog Shon; Soo Mi Yang; Jae Jo Lee // GSTF Journal on Computing;2011, Vol. 1 Issue 2, p180 

    This paper proposes a new architecture for EIA-709.1 protocol implementation. The protocol is conventionally implemented with the proprietary processor and language, Neuron chip and Neuron C, respectively, where the Neuron chip consists of 3 processors inside. The proposed architecture uses only...

  • An Efficient Retargetable Simulator SIM-A for ASIP DSE and Validation with RISC and VLIW based Processors. Kumar Jain, Manoj; Kumar Ranka, Gajendra // International Journal of Advanced Research in Computer Science;Mar/Apr2012, Vol. 3 Issue 2, p11 

    General Purpose Processor (GPP) provides high application flexibility but at a high cost in terms of more silicon area, high power consumption and low performance. In systems where high application flexibility is not required, it is possible to trade off flexibility for lower cost by tailoring...

  • HARDWARE MODELLING OF A 32-BIT, SINGLE CYCLE RISC PROCESSOR USING VHDL. Omran, Safaa S.; Mahmood, Hadeel S. // International Conference on Information Technology;2013, p1 

    In this research, the VHDL (Very high speed IC Hardware Description Language) hardware modelling of the complete design of a 32-bit MIPS (Microprocessor without Interlocked Pipeline Stages), single cycle RISC (Reduced Instruction Set Computer) processor is presented. First the work defines the...

  • 32-bit MCU with CAN or 12C interfaces.  // Electronics Weekly;9/24/2003, Issue 2116, p38 

    The company Sunrise Electronics has added to its NEC range of Risc microcontrollers members of the recently introduced S&95;Line range which is designed for memory-hungry embedded and EMI-sensitive applications.

  • Reduced-Precision Redundancy on FPGAs. Pratt, Brian; Fuller, Megan; Wirthlin, Michael // International Journal of Reconfigurable Computing;2011, p1 

    Reduced-precision redundancy (RPR) has been shown to be a viable alternative to triple modular redundancy (TMR) for digital circuits. This paper builds on previous research by offering a detailed analysis of the implementation of RPR on FPGAs to improve reliability in soft error environments....

  • Experiment Centric Teaching for Reconfigurable Processors. Lagadec, Loïc; Picard, Damien; Corre, Youenn; Lucas, Pierre-Yves // International Journal of Reconfigurable Computing;2011, p1 

    This paper presents a setup for teaching configware to master students. Our approach focuses on experiment and leaning-bydoing while being supported by research activity. The central project we submit to students addresses building up a simple RISC processor, that supports an extensible...

  • MIPS cores win Dolby approval.  // Electronics Weekly;8/16/2006, Issue 2254, p4 

    The article reports on the approval of MIPS32 processor cores by Dolby Digital. MIPS Technologies' 24k and 34k codes have been approved for Dolby Digital Plus audio codecs. MIPS is the first core firm to provide approved codecs. Dolby has particularly designed the codecs for the MIPS cores....

  • Not exclusive.  // Electronic News (10616624);8/14/95, Vol. 41 Issue 2078, p4 

    Suggests that LSI Logic may be considering an Advanced RISC Machines (ARM) processor core for its CoreWare family. VLSI Technology and the licensing of the Advanced RISC Machines processor for its Ruby family of devices; Application specific integrated circuits (ASIC).


Read the Article


Sorry, but this item is not currently available from your library.

Try another library?
Sign out of this library

Other Topics