TITLE

Comparison of Three Techniques for Leakage Current Minimization in CMOS VLSI Circuit in 90 nm Technology

AUTHOR(S)
Mukherjee, Debasis; Reddy, B. V. R.; Perveen, Gulnar; Kumar, Niti; Noor, Arti
PUB. DATE
November 2010
SOURCE
International Journal on Recent Trends in Engineering & Technolo;Nov2010, Vol. 4 Issue 4, p162
SOURCE TYPE
Academic Journal
DOC. TYPE
Article
ABSTRACT
Today VLSI circuit fabrication technology has reached in nanometer dimension. When CMOS technology superseded BJT technology, very low leakage current was one of the main advantages for CMOS circuits. But in nm range, as threshold voltage, channel length, and gate oxide thickness are reduced, leakage current issue is becoming one of the major problems. On the other side, due to huge use of portable devices, low power circuit is in high demand. In this paper simulation results of single cell SRAM are shown. Three different techniques are tested by 90 nm technology file on Cadence platform. Leakage current has significantly reduced from nA range to pA range after applying the techniques.
ACCESSION #
82678232

 

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