Ghorbani, Ali; Sarkhosh, Mehdi; Fayyazi, Elnaz; Mahmoudi, Neda; Keshavarzian, Peiman
June 2012
International Journal of VLSI Design & Communication Systems;Jun2012, Vol. 3 Issue 3, p33
Academic Journal
Presenting a novel full adder cell will be increases all the arithmetic logic unit performance. In this paper, We present two new full adder cell designs using carbon nanotube field effect transistors (CNTFETs). In the first design we have 42 transistors and 5 pull-up resistance so that we have achieved an improvement in the output parameters. Simulations were carried out using HSPICE based on the CNTFET model with 0.9V VDD. The denouments results in that we have a considerable improvement in power, Delay and power delay product than the previous works.


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