Instruction scheduling methods and phase ordering framework for VLIW DSP processors with distributed register files

Wu, Chung-Ju; Lin, Yu-Te; Lee, Jenq-Kuen
September 2012
Journal of Supercomputing;
Digital signal processors (DSPs) with very long instruction word (VLIW) data-path architectures are increasingly being deployed on embedded devices in video and other multimedia processing applications. To reduce the power consumption and design cost of VLIW DSP processors, distributed register files and multi-bank register architectures are being adopted to eliminate the amount of read/write ports associated with register files. This presents challenges for compilers attempting to generate efficient codes. In this paper we present an instruction scheduling method and phase ordering framework for such an architecture based on the well-known PALF scheme. The PALF scheme first performs bank partitioning followed by register allocation and then instruction scheduling. Our contribution includes the insertion of a pseudo instruction scheduler that performs bank assignment analysis before PALF assignment. We also enhance the PALF scheme by utilizing the program graph with cycle information generated by our pseudo scheduler. Finally, a ping-pong-aware scheduling policy is used in the scheduling phases to address the issue of limited temporal connectivities among register banks for DSP processors. Experiments were performed on an instruction set simulator for Parallel Architecture Core DSP processors based on the Open64 compiler infrastructure. Preliminary experiments with the EEMBC and MiBench benchmarks show that a compiler based on our proposed scheme for handling hardware constraints of VLIW scheduling on distributed register files exhibits performance superior to that of the PALF scheme.


Related Articles

  • Exploring the speedups of embedded microprocessor systems utilizing a high-performance coprocessor data-path. Galanis, Michalis; Dimitroulakos, Gregory; Goutis, Costas // Journal of Supercomputing;Mar2007, Vol. 39 Issue 3, p251 

    The speedups achieved in a generic microprocessor system by employing a high-performance data-path are presented. The data-path acts as a coprocessor that accelerates time critical code segments, called kernels, thereby increasing the overall performance. The data-path has been previously...

  • Communication Management Unit : Single Solution of Voice and Data Routing Unit. Shankar, Ravi // Defence Science Journal;Mar2013, Vol. 63 Issue 2, p181 

    Challenges faced by present avionics systems are low weight, less power, low volume, high mean time between failure and low mean time to repair. This paper is a feasibility study for single solution of voice and data switching/routing unit. This paper presents a new architecture for voice and...

  • Next-Gen DSPs. Small, Charles // Electronic News;11/01/99, Vol. 45 Issue 44, p53 

    Presents information on digital signal processing (DSP) microprocessors. Distinction between DSP processors and control processors; Hardware and instructions for DSP processors; Plans of cellular phone makers to combine DSP processor and microcontroller into one device; Problems with the...

  • Virtually Develop DSPs. Wong, William // Electronic Design;5/13/2002, Vol. 50 Issue 10, p29 

    Focuses on Wind River Inc.'s VSPWorks for use in the development of multiple digital signal processor. Interprocess communication services; Integration of VSPWorks with VxWorks; Price.

  • DSP extension outmuscles integer unit. Levy, Markus // EDN;07/20/2000, Vol. 45 Issue 15, p28 

    Features the Xtensa III configurable processor developed by Tensilica. Offering of an upgraded Tensilica instruction-extension compiler for digital signal processing; Automated capability for configuring system-development environments and third-party RTOS.

  • New audio DSP from Motorola.  // Electronic News;01/12/98, Vol. 44 Issue 2201, p18 

    Presents a schematic diagram of Motorola's DSP56362 digital signal processor. Introduction of the processor at the Winter Consumer Electronics Show in Las Vegas, Nevada.

  • Legacy CPUs Aren't Cores. Terwilliger, Bob // Electronic News;06/05/2000, Vol. 46 Issue 23, p8 

    Discusses the problems faced by microprocessor designers with core vendors and silicon foundries. Function of microprocessors; Production of central processing unit and digital signal processing.

  • Macro-programmable reconfigurable stream processor for collaborative manufacturing systems. Kirischian, Valeri; Geurkov, Vadim; Chun, Pill; Kirischian, Lev // Journal of Intelligent Manufacturing;Dec2008, Vol. 19 Issue 6, p723 

    Growing demand for high speed processing of streamed data (e.g. video-streams, digital signal streams, communication streams, etc.) in the advanced manufacturing environments requires the adequate cost-efficient stream-processing platforms. Platforms based on the embedded microprocessors often...

  • VLSI Implementation of Heterogeneous Adder for Performance Optimization. Singh, Raminder Preet Pal; Chaturvedi, Ashish // International Journal of Computer Applications;8/1/2012, Vol. 51, p37 

    An Adder is one of the significant hardware blocks in most digital systems such as digital signal processors and microprocessors etc. Over the last few decades lot of research have been carried out in order to design an efficient adder circuits in terms of compactness, high speed and low power...


Read the Article


Sorry, but this item is not currently available from your library.

Try another library?
Sign out of this library

Other Topics