CSP and Flip Chip Assembly Using Tacky Flux

Nikeschina, Marina; Emmen, Hans
October 2002
Circuits Assembly;Oct2002, Vol. 13 Issue 10, p40
Trade Publication
Investigates the relationship between placement accuracy and formation of solder joints. Effects of component pitch and board layout on the placement accuracy of chip-scale packages; Methods used for high-volume electronics circuits manufacturing; Placement limitations for copper-defined footprints.


Related Articles

  • Design for Reliability of Stacked Die CSPs. Tong Yan Tee // Advanced Packaging;Jul2004, Vol. 13 Issue 7, p37 

    Focuses on the demand for chip scale packages for portable and handheld electronic applications. Reduction of the footprint; Packaging of the microelectromechanical system accelerometers; Assessment of the board-level solder joint reliability of stacked die.

  • Influence of Interfacial Reaction Layer on Reliability of Chip-Scale Package Joint from Using Sn-37Pb and Sn-8Zn-3Bi Solder. Chung-Hee Yu; Kyung-Seob Kim; Hyung-Il Kim; Hyo-Joeng Jeon // Journal of Electronic Materials;Feb2005, Vol. 34 Issue 2, p161 

    The microstructure of Sn-37Pb and Sn-8Zn-3Bi solders and the full strength of these solders with an Au/Ni/Cu pad under isothermal aging conditions were investigated. The full strengths tended to decrease as the aging temperature and time increased, regardless of the properties of the solders....

  • Effect of Thermal Aging on Drop Performance of Chip Scale Packages with SnAgCu Solder Joints on Cu Pads. Weiqun Peng; Marques, Marco Elisio // Journal of Electronic Materials;Dec2007, Vol. 36 Issue 12, p1679 

    Because of the trend of miniaturization, the drop performance of portable electronic devices is becoming increasingly critical. This study was focused on the influential factors in the drop performance of chip scale packages (CSPs) with Cu/SnAgCu solder joints after thermal aging. Assembled CSP...

  • PRINTING MINIATURIZED COMPONENTS. Ashmore, Clive; Schake, Jeff // SMT: Surface Mount Technology;Aug2007, Vol. 21 Issue 8, p11 

    The article discusses the essence of advances in component packaging, high-density board fabrication, and system-level integration to miniaturization of electronic products. It is cited that in practice and production by applying advanced packaged technologies, satisfactory results have been...

  • DESIGN AND FAB TIPS for Improving Solder Mask Registration. HIEN LY // Printed Circuit Design & Manufacture;Jan2009, Vol. 26 Issue 1, p28 

    The article provides several printed circuit board (PCB) design and fabrication tips for improving solder mask registration on fine-pitch ball-grid array (BGA) and chip-scale packages (CSP). Companies are advised to create specifications in the fabrication notes to indicate unique solder mask...

  • The Effects of Additives to SnAgCu Alloys on Microstructure and Drop Impact of Reliability of Solder Joints. Weiping Liu; Ning-Cheng Lee // JOM: The Journal of The Minerals, Metals & Materials Society (TM;Jul2007, Vol. 59 Issue 7, p26 

    The impact reliability of solder joints in electronic packages is critical to the lifetime of electronic products, especially those portable devices using area array packages such as ball-grid array (BGA) and chip-scale packages (CSP). Currently, SnAgCu (SAC) solders are most widely used for...

  • The Observation and Simulation of Sn-Ag-Cu Solder Solidification in Chip-Scale Packaging. Keun-Soo Kim; Suganuma, Katsuaki; Jong-Min Kim; Chi-Won Hwang // JOM: The Journal of The Minerals, Metals & Materials Society (TM;Jun2004, Vol. 56 Issue 6, p39 

    The formation of solidification defects in lead-free soldering is greatly influenced by material factors as well as the design of circuit assemblies. To establish ideal processing conditions and design concepts for sound soldering structures, defect formation in Sn-Ag-Cu for various types of...

  • The search for a "super QFN" package. Chait, Arthur L. // Solid State Technology;Jul2011, Vol. 54 Issue 7, p38 

    The article focuses on search for super quad flat no lead (QFN) packages by leadframes. It states that QFN package is a cost effective semiconductor packages and are near chip scale packages with lands' perimeter for solder connections to the circuit board. It says that there are technologies...

  • Modeling of moisture over-saturation and vapor pressure in die-attach film for stacked-die chip scale packages. Chen, Liangbiao; Adams, Jeremy; Chu, Hsing-Wei; Fan, Xuejun // Journal of Materials Science: Materials in Electronics;Jan2016, Vol. 27 Issue 1, p481 

    Die-attach film failure during soldering reflow is of particular concern for reliability of 3D ultra-thin stacked-die chip scale packages (CSPs), as extremely high vapor pressure can be generated from vaporized moisture to cause severe damages. Under rapid heating, pressure-driven moisture vapor...


Read the Article


Sorry, but this item is not currently available from your library.

Try another library?
Sign out of this library

Other Topics