Managing CSP Underfill Processes
- The future role of chip-scale packaging in COTS reliability. Gurnett, Keith; Adams, Tom // Military & Aerospace Electronics;May2001, Vol. 12 Issue 5, p3
Discusses the impact of ever-shrinking components for electronic systems designs on the development of chip scale packages (CSP). Use of CSP in commercial off-the-shelf military and high-reliability applications; Advantages of using CSP; History of CSP.
- Packing and Stacking. Fjelstad, Joe // Electronic News;01/22/2001, Vol. 47 Issue 4, p48
Deals with the introduction of chip scale packages in an attempt to reduce the size of electronics products while maintaining or increasing their functionality. Features of chip scale packages; Concept of chip stacking; Background on the concept of maximum percent active silicon; Methods of...
- Stacked Die CSPs: Beyond Chip Size. Tessier, Theodore // Electronic News;1/21/2002, Vol. 48 Issue 4, p21
Focuses on the market acceptance of stacked die packaging technologies for use in cellular phone and handheld applications. Information on the emergence of high-volume stacked died packaging applications; Role of chip-scale packages in the improvement of silicon efficiency for single-die...
- CSP and Flip Chip Assembly Using Tacky Flux. Nikeschina, Marina; Emmen, Hans // Circuits Assembly;Oct2002, Vol. 13 Issue 10, p40
Investigates the relationship between placement accuracy and formation of solder joints. Effects of component pitch and board layout on the placement accuracy of chip-scale packages; Methods used for high-volume electronics circuits manufacturing; Placement limitations for copper-defined...
- Reliability Requirements for Portable Electronics. Demmin, Jeffrey C. // Advanced Packaging;Oct2003, Vol. 12 Issue 10, p29
Discusses the reliability requirements for portable electronic packaging and chip scale packaging (CSP). Package reliability in portable application; Aspects of CSP design; Methods for reliability testing; Performance and density benefits from packaging technologies.
- ChipPAC Offers 5-Die Stacked CSP. // Electronic News;4/28/2003, Vol. 49 Issue 17, pN.PAG
Reports the launching of the four- and five-die stacked computer chip scale package from ChipPAC Inc. Semiconductors that could be housed in the package; Featurs; Growth of the market for stacked die packages.
- Challenges Ahead for 3-D CSP Suppliers. // Advanced Packaging;Jul2004, Vol. 13 Issue 7, p10
Reports on the result of a study indicating that three-dimensional (3-D) chip scale packaging solutions will play an increasing role in future generations of mobile electronics in the U.S. Features of current 3-D chip scale packaging; Benefits derived from using 3-D scale packaging solutions;...
- Chipping Away the Yield. Collier, Terence // Circuits Assembly;Nov2003, Vol. 14 Issue 11, p48
Sacrificing cost for real estate, chip-scale packages (CSPs) are projected to reach up to 30% of the market share of all packages sold in only a few years. Currently, CSP assemblies represent 10% of the market; the traditional, larger packages retain a 90% market share. To penetrate the market,...
- Solder Ball Endurance. // Advanced Packaging;Sep2003, Vol. 12 Issue 9, p50
Discusses the material and process effects of the ball shear strength in packaging. Environmental challenges faced by ball grid array and chip scale package; Three most common root causes leading to package and device failure; Establishment of qualification procedures and requirements to...