TITLE

A Reconfigurable Switch Architecture to Enhance Reliability of Network-on-Chips

AUTHOR(S)
Shirmohammadi, Z.; Jalal, M.; Patooghy, A.; Miremadi, S. G.
PUB. DATE
November 2010
SOURCE
International Conference on Real-Time & Embedded Systems;Nov2010, pR-98
SOURCE TYPE
Conference Paper
DOC. TYPE
Article
ABSTRACT
Switches and communication links of Network on Chips (NoCs) are highly vulnerable to transient faults due to the use of nano-scale VLSI technologies in fabrication of NoCs. This paper proposes a reconfigurable switch architecture which is capable of operating in four configurations with different levels of reliability. This is done by the use of a local configuration controller logic which is fully protected against transient faults. When a controller detects a high error rate situation, it configures the switch to a high reliability mode and vice versa. Reconfiguration policy is designed in a way which minimizes the imposed performance and power overheads to the switch. Evaluations are done by a cycle accurate NoC simulator with Orion patch for power estimation. Simulation results show a noticeable reliability improvement with a negligible performance overhead. In addition, power saving of at least 20% is achieved by the proposed architecture.
ACCESSION #
65648201

 

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