TITLE

Low leakage current Cu(Ti)/SiO[sub 2] interconnection scheme with a self-formed TiO[sub x] diffusion barrier

AUTHOR(S)
Liu, C. J.; Chen, J. S.
PUB. DATE
April 2002
SOURCE
Applied Physics Letters;4/15/2002, Vol. 80 Issue 15, p2678
SOURCE TYPE
Academic Journal
DOC. TYPE
Article
ABSTRACT
Electrical and material properties of Cu(0.02 wt % Ti) alloy and pure Cu films deposited on SiO[sub 2]/Si are explored. Current–voltage measurement using metal–oxide–semiconductor (MOS) capacitor structure reveals low leakage current (10[sup -8] A/cm[sup 2]) for capacitors with as-deposited Cu(0.02 wt % Ti) and pure Cu metal gates. However, after annealing at 700 °C in a vacuum, leakage current of MOS capacitors using a pure Cu gate shows a dramatic rise of leakage current at a low electrical field, while the leakage current of capacitors with Cu(0.02 wt % Ti) gate stays at ∼10[sup -7] A/cm[sup 2]. Concurrently, the resistivity of annealed Cu(0.02 wt % Ti) is reduced to 2.5 μΩ cm, which is only slightly greater than the resistivity of as-sputtered pure Cu films. X-ray photoelectron spectroscopy indicates that a TiO[sub x] layer has formed at the Cu(0.02 wt % Ti)/SiO[sub 2] interface after annealing and Auger electron spectrometry depth profiles show less interdiffusion at the Cu(0.02 wt % Ti)/SiO[sub 2] interface than the Cu/SiO[sub 2] interface. The correlation between leakage current reliability and the interfacial reaction upon annealing is discussed. © 2002 American Institute of Physics.
ACCESSION #
6483055

 

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