Impact of atomic-layer-deposited TiN on the gate oxide quality of W/TiN/SiO[sub 2]/Si metal–oxide–semiconductor structures

Park, Dae-Gyu; Lim, Kwan-Yong; Cho, Heung-Jae; Cha, Tae-Ho; Yeo, In-Seok; Roh, Jae-Sung; Park, Jin Won
April 2002
Applied Physics Letters;4/8/2002, Vol. 80 Issue 14, p2514
Academic Journal
We demonstrate the impact of atomic-layer-deposited TiN gate on the characteristics of W/TiN/SiO[sub 2]/p-Si metal–oxide–semiconductor (MOS) systems. Damage-free gate oxide quality was attained with atomic-layer-deposition (ALD)–TiN as manifested by an excellent interface trap density (D[sub it]) as low as ∼4×10[sup 10] eV[sup -1] cm[sup -2] near the Si midgap. ALD–TiN improved the D[sub it] level of MOS systems on both thin SiO[sub 2] and high-permittivity (high-k) gate dielectrics. The leakage current of a MOS capacitor gated with ALD–TiN is remarkably lower than that with sputter-deposited TiN and poly-Si gate at the similar capacitance equivalent thickness (CET). Less chlorine content in ALD–TiN films appears to be pivotal in minimizing the CET increase against postmetal anneal and improving gate oxide reliability, paving a way for the direct metal gate process. © 2002 American Institute of Physics.


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