TITLE

Improving SiO[sub 2]/SiGe interface of SiGe p-metal–oxide–silicon field-effect transistors using water vapor annealing

AUTHOR(S)
Ngai, T.; Chen, X.; Chen, J.; Banerjee, S. K.
PUB. DATE
March 2002
SOURCE
Applied Physics Letters;3/11/2002, Vol. 80 Issue 10, p1773
SOURCE TYPE
Academic Journal
DOC. TYPE
Article
ABSTRACT
SiGe p-metal–oxide–silicon field-effect transistors (p-MOSFETs) were fabricated with ultrathin thin (∼20 Å) remote plasma chemical vapor deposition gate oxides deposited directly on SiGe. A low temperature water vapor annealing was used to improve the SiO[sub 2]/SiGe interface and performance of SiGe p-MOSFETs. After the wet annealing, dangling Si and Ge bonds at the interface are passivated by atomic hydrogen, the threshold voltage of SiGe p-MOSFETs decreases from -0.39 to -0.20 V, the subthreshold slope from 117 to 87 mV/dec, and more than 20% output current enhancement is observed in these SiGe p-MOSFETs compared with Si control devices. © 2002 American Institute of Physics.
ACCESSION #
6281328

 

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