Mobility Enhancement Technology for Scaling of CMOS Devices: Overview and Status

Song, Yi; Zhou, Huajie; Xu, Qiuxia; Luo, Jun; Yin, Haizhou; Yan, Jiang; Zhong, Huicai
July 2011
Journal of Electronic Materials;Jul2011, Vol. 40 Issue 7, p1584
Academic Journal
The aggressive downscaling of complementary metal-oxide-semiconductor (CMOS) technology to the sub-21-nm technology node is facing great challenges. Innovative technologies such as metal gate/high- k dielectric integration, source/drain engineering, mobility enhancement technology, new device architectures, and enhanced quasiballistic transport channels serve as possible solutions for nanoscaled CMOS. Among them, mobility enhancement technology is one of the most promising solutions for improving device performance. Technologies such as global and process-induced strain technology, hybrid-orientation channels, and new high-mobility channels are thoroughly discussed from the perspective of technological innovation and achievement. Uniaxial strain is superior to biaxial strain in extending metal-oxide-semiconductor field-effect transistor (MOSFET) scaling for various reasons. Typical uniaxial technologies, such as embedded or raised SiGe or SiC source/drains, Ge pre-amorphization source/drain extension technology, the stress memorization technique (SMT), and tensile or comprehensive capping layers, stress liners, and contact etch-stop layers (CESLs) are discussed in detail. The initial integration of these technologies and the associated reliability issues are also addressed. The hybrid-orientation channel is challenging due to the complicated process flow and the generation of defects. Applying new high-mobility channels is an attractive method for increasing carrier mobility; however, it is also challenging due to the introduction of new material systems. New processes with new substrates either based on hybrid orientation or composed of group III-V semiconductors must be simplified, and costs should be reduced. Different mobility enhancement technologies will have to be combined to boost device performance, but they must be compatible with each other. The high mobility offered by mobility enhancement technologies makes these technologies promising and an active area of device research down to the 21-nm technology node and beyond.


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