TITLE

A Taxonomy of Reconfigurable Single-/Multiprocessor Systems-on-Chip

AUTHOR(S)

Göhringer, Diana; Perschke, Thomas; Hübner, Michael; Becker, Jürgen

PUB. DATE

January 2009

SOURCE

International Journal of Reconfigurable Computing;2009, p1

SOURCE TYPE

Academic Journal

DOC. TYPE

Article

ABSTRACT

Runtime adaptivity of hardware in processor architectures is a novel trend, which is under investigation in a variety of research labs all over the world. The runtime exchange of modules, implemented on a reconfigurable hardware, affects the instruction flow (e.g., in reconfigurable instruction set processors) or the data flow, which has a strong impact on the performance of an application. Furthermore, the choice of a certain processor architecture related to the class of target applications is a crucial point in application development. A simple example is the domain of high-performance computing applications found in meteorology or high-energy physics, where vector processors are the optimal choice. A classification scheme for computer systems was provided in 1966 by Flynn where single/multiple data and instruction streams were combined to four types of architectures. This classification is now used as a foundation for an extended classification scheme including runtime adaptivity as further degree of freedom for processor architecture design. The developed scheme is validated by a multiprocessor system implemented on reconfigurable hardware as well as by a classification of existing static and reconfigurable processor systems.

ACCESSION #

47915545

Tags: SYSTEMS on a chip;  MULTIPROCESSORS;  MULTICORE processors (Computers);  EMBEDDED computer systems;  SYSTEMS design;  SYSTEMS development;  COMPUTER systems;  COMPUTER architecture;  SYSTEMS engineering;  ADAPTIVE computing systems

 

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