Impact of device configuration on the temperature instability of Al–Zn–Sn–O thin film transistors

Jae Kyeong Jeong; Shinhyuk Yang; Doo-Hee Cho; Sang-Hee Ko Park; Chi-Sun Hwang; Kyoung Ik Cho
September 2009
Applied Physics Letters;9/21/2009, Vol. 95 Issue 12, p123505
Academic Journal
We compared the effect of the temperature on the device stability of Al–Zn–Sn–O (AZTO) thin film transistors (TFTs) with top gate and bottom gate architectures. While the bottom gate device without any passivation layer on the AZTO channel layer showed a large threshold voltage (Vth) shift of 1.6 V after heating it from 298 to 398 K, the naturally passivated top gate device exhibited a smaller Vth shift of 0.6 V. This different behavior is discussed based on the concept of the thermal activation energy of the subthreshold drain current. It is proposed that the suitable passivation and lower interfacial trap density for the top gate TFT are responsible for its superior temperature stability compared to the bottom gate device.


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