TITLE

Properties of latent interface-trap buildup in irradiated metal-oxide-semiconductor transistors determined by switched bias isothermal annealing experiments

AUTHOR(S)
Jaksic, Aleksandar B.; Pejovic, Momcilo M.; Ristic, Goran S.
PUB. DATE
December 2000
SOURCE
Applied Physics Letters;12/18/2000, Vol. 77 Issue 25
SOURCE TYPE
Academic Journal
DOC. TYPE
Article
ABSTRACT
Isothermal annealing experiments with switched gate bias have been performed to determine the properties of the latent interface-trap buildup during postirradiation annealing of metal-oxide-semiconductor transistors. It has been found that a bias-independent process occurs until the start of the latent interface-trap buildup. During the buildup itself, oxide-trap charge is not permanently neutralized, but is temporarily compensated. © 2000 American Institute of Physics.
ACCESSION #
4414207

 

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