Random telegraph signal noise in gate-all-around silicon nanowire transistors featuring Coulomb-blockade characteristics

Jing Zhuge; Liangliang Zhang; Runsheng Wang; Ru Huang; Dong-Won Kim; Donggun Park; Yangyuan Wang
February 2009
Applied Physics Letters;2/23/2009, Vol. 94 Issue 8, p083503
Academic Journal
Random telegraph signal (RTS) noise is experimentally investigated in silicon nanowire transistors (SNWTs) fabricated with complementary-metal-oxide-semiconductor compatible top-down approach. The observed RTS is found to have Coulomb-blockade characteristics rather than those described by conventional Shockley–Read–Hall theory. The capture and emission time constants of oxide traps strongly depend on the gate bias due to strong quantum confinement and enhanced electrical field in nanowire structures. Amplitude of single RTS in SNWTs is found within 10%, while large amplitude of multilevel RTS up to 34% at room temperature is observed due to the ultranarrow channel and the behavior of independent multitraps in SNWTs. Widely spread time constants of oxide traps and slow RTS of very long-time constants (several hundred seconds) are also observed in SNWTs.


Related Articles

  • Impact of Advanced Gate Stack Engineering On Low Frequency Noise Performances of Planar Bulk CMOS transistors. Mercha, A.; Okawa, H.; Akheyar, A.; Simoen, E.; Nakabayashi, T.; Hoffmann, T. Y. // AIP Conference Proceedings;4/23/2009, Vol. 1129 Issue 1, p277 

    This paper discusses on the impact of gate stack engineering on the low-frequency noise performance of state-of-the-art deep submicron planar CMOS technologies. Focus is on the scaling of the Equivalent Oxide Thickness (EOT) in high-k gate oxides in combination with metal gates, requiring the...

  • Design of SIPC based LC-QVCO in 0.18 μm CMOS Technology and the Impact of Coupling Factor, K. Ramiah, Harikrishnan; Kanesan, Jeevan; Zulkifli, Tun Zainal Azni // IETE Journal of Research (Medknow Publications & Media Pvt. Ltd.;Jan/Feb2012, Vol. 58 Issue 1, p28 

    This paper presents the design of a source injection parallel coupled (SIPC) quadrature voltage-controlled oscillator (QVCO), realized with pMOS transistors, relaxing the sensitivity to substrate-induced noise and flicker noise, 1 f effect. A stacked planar spiral inductor exhibiting a Q factor...

  • Noise Performance at Cryogenic Temperature of Microwave SiGeC Low Noise Amplifier using BiCMOS Technology. Pruvost, S.; Delcourt, S.; Danneville, F.; Telliez, I.; Dambrine, G.; Laurens, M.; Monroy, A. // AIP Conference Proceedings;2005, Vol. 780 Issue 1, p509 

    This work presents a 1-stage Low Noise Amplifier (LNA) realized using a 0.13μm SiGe:C Heterojunction Bipolar Transistor (HBT). Measured under cryogenic temperature this LNA exhibits a noise figure of 1.8dB at 78K and 40GHz which corresponds to 70% improvement compared with result achieved at...

  • Application of Taguchi Method in the Optimization of Process Variation for 32nm CMOS Technology. Elgomati, H. A.; Majlis, B. Y.; Ahmad, I.; Salehuddin, F.; Hamid, F. A.; Zaharim, A.; Apte, P. R. // Australian Journal of Basic & Applied Sciences;2011, Vol. 5 Issue 7, p346 

    In this paper, we investigate the effect of four process parameters namely HALO implantation, compensation implantations, SiO2 thickness and silicide annealing time on threshold voltage (VTH) in complementary metal oxide semiconductor (CMOS) technology. The setting of process parameters were...

  • DFM of Strained-Engineered MOSFETs Using Technology CAD. Maiti, T. K.; Maiti, C. K. // American Journal of Engineering & Applied Sciences;2010, Vol. 3 Issue 4, p683 

    The article presents a study which explores the Design Factor Manufacturing (DFM) of strained-engineered metal oxide semiconductor field-effect transistors (MOSFETs) using technology computer aided design (TCAD). The Synopsys Sentaurus Process simulation tool was used to induce uniaxial stress...

  • Extraction and Simulation of Intra-gate Defects Affecting CMOS Libraries.  // Journal of Computers;Oct2010, Vol. 5 Issue 10, p1468 

    No abstract available.

  • Chromeless phase-shift masks used for sub-100nm SOI CMOS transistors. Fritze, Michael; Astolfi, David K.; Yost, Donna-Ruth W.; Wyatt, Peter W.; Liu, Hua-Yu // Solid State Technology;Jul2000, Vol. 43 Issue 7, p116 

    Features a study which applied chromeless phase-shift masks to sub-100 nanometer-gate-length fully depleted silicon on insulator complementary metal oxide semiconductor transistor fabrication. Experimentation for chromeless phase-shift mask application; Imaging and pattern transfer of dense...

  • Self-aligned placement of biologically synthesized Coulomb islands within nanogap electrodes for single electron transistor. Kumagai, Shinya; Yoshii, Shigeo; Matsukawa, Nozomu; Nishio, Kazuaki; Tsukamoto, Rikako; Yamashita, Ichiro // Applied Physics Letters;2/23/2009, Vol. 94 Issue 8, p083103 

    Biological synthesis and self-aligned placement of a Coulomb island was demonstrated for single electron transistor (SET) fabrication using a cage-shaped protein, apoferritin. Homogenous [lowercase_phi_synonym]7 nm Co3O4 and In oxide nanoparticles (NPs) were synthesized utilizing the apoferritin...

  • Pushing energy savings in adiabatic logic by carbon-nanotube field effect transistors. Teichmann, P.; Friederich, C.; Schmitt-Landsiedel, D. // Advances in Radio Science;2011, Vol. 9, p215 

    For the first time carbon nanotube (CNT) transistor based adiabatic logic (AL) was analyzed in this work and compared to CNT based static CMOS (CCNT). Static CCNT inverters are used as a reference and compared to inverters in the AL families Efficient Charge Recovery Logic (ECRL) and Positive...


Read the Article


Sorry, but this item is not currently available from your library.

Try another library?
Sign out of this library

Other Topics