Parallel Form of the Pipelined Intermediate Architecture for Two-dimensional Discrete Wavelet Transform

Koko, Ibrahim Saeed; Agustiawan, Herman
May 2009
IAENG International Journal of Computer Science;May2009, Vol. 36 Issue 2, p1
Academic Journal
A lifting-based VLSI architecture for twodimensional discrete wavelet transform (2-D DWT) for 5/3 and 9/7 algorithms, called, pipelined intermediate architecture was proposed by Ibrahim et al., which aim at reducing power consumption of the overlapped external memory access without using the expensive line-buffer. In this paper, we explore parallelism in order to best meet real-time applications of 2-D DWT with demanding requirements in terms of speed, throughput, and power consumption. Therefore, 2-parallel and 3-parallel form of the single pipelined intermediate architecture are proposed. The 2-parallel and 3-parallel pipelined intermediate architectures achieve speedup factors of 2 and 3, respectively, as compared with single pipelined intermediate architecture proposed by Ibrahim et al.


Related Articles

  • Efficient VLSI Architecture for Lifting-Based Discrete Wavelet Packet Transform. Babu, M. Suresh; Babu, K. Ashok; Pillai, G. Kesavan // Advances in Computational Sciences & Technology;Jun2010, Vol. 3 Issue 2, p137 

    This brief presents a novel very large-scale integration (VLSI) architecture for discrete wavelet packet transform (DWPT). By exploiting the in-place nature of the DWPT algorithm, this architecture has an efficient pipeline structure to implement high-throughput processing without any on-chip...

  • Analysis and Design of a Context Adaptable SAD/MSE Architecture. Sudarsanam, Arvind; Dasu, Aravind; Vaithianathan, Karthik // International Journal of Reconfigurable Computing;2009, p1 

    Design of flexible multimedia accelerators that can cater to multiple algorithms is being aggressively pursued in the media processors community. Such an approach is justified in the era of sub-45 nm technology where an increasingly dominating leakage power component is forcing designers to make...

  • FPGA IMPLEMENTATION OF EFFICIENT VLSI ARCHITECTURE FOR FIXED POINT 1-D DWT USING LIFTING SCHEME. Sowjanya, Durga; Srinivas, K. N. H.; Ganapathi, P. Venkata // International Journal of VLSI Design & Communication Systems;Aug2012, Vol. 3 Issue 4, p37 

    In this paper, a scheme for the design of area efficient and high speed pipeline VLSI architecture for the computation of fixed point 1-d discrete wavelet transform using lifting scheme is proposed. The main focus of the scheme is to reduce the number and period of clock cycles and efficient...

  • Discrete Wavelet Transform and Modified Chaotic Key-based Algorithm for Image Encryption and its VLSI Realization. Rao, K. Deergha; Gangadhar, Ch. // IETE Journal of Research (Medknow Publications & Media Pvt. Ltd.;May/Apr2012, Vol. 58 Issue 2, p114 

    Chaos-based encryption may offer new quality in secure data transmission. A recently proposed Chaotic Key-Based Algorithm (CKBA) has been shown to be unavoidably susceptible to chosen/known plaintext attacks and ciphertextonly attacks. In this paper, Discrete wavelet transform and Modified...

  • The Segmented-Matrix Algorithm for Haar Discrete Wavelet Transform. PO-YUEH CHEN; EN-CHI LIAO; CHUNG-WEI LIANG // Journal of Information Science & Engineering;Jul2008, Vol. 24 Issue 4, p1273 

    Discrete wavelet transform (DWT) is an efficient tool for multi-resolution decomposition of images. It has been shown to be very promising due to its high compression ratio and self-similar data structure. Conventionally a 2-D DWT is accomplished by performing two 1-D operations: one along the...

  • A Reconfigurable Switch Architecture to Enhance Reliability of Network-on-Chips. Shirmohammadi, Z.; Jalal, M.; Patooghy, A.; Miremadi, S. G. // International Conference on Real-Time & Embedded Systems;Nov2010, pR-98 

    Switches and communication links of Network on Chips (NoCs) are highly vulnerable to transient faults due to the use of nano-scale VLSI technologies in fabrication of NoCs. This paper proposes a reconfigurable switch architecture which is capable of operating in four configurations with...

  • FUNCTIONAL TEST GENERATOR FOR VLSI CIRCUITS. Hudec, Ján // Proceedings of the International Conference on Systems for Autom;2005, p46 

    This paper deals with the design and implementation of a universal functional test generator for VLSI circuits. Our approach to test generation - the functional test generation method - is based on knowledges and functional description of VLSI systems at functional VHDL level and the algorithm...

  • AN EFFICIENT APPROACH FOR FOUR-LAYER CHANNEL ROUTING IN VLSI DESIGN. Khan, Ajoy Kumar; Das, Bhaskar; Bayen, Tapas Kumar // International Journal of VLSI Design & Communication Systems;Oct2012, Vol. 3 Issue 5, p147 

    Channel routing is a key problem in VLSI physical design. The main goal of the channel routing problem is to reduce the area of an IC chip. If we concentrate on reducing track number in channel routing problem then automatically the area of an IC chip will be reduced. Here, we propose a new...

  • TEST POWER OPTIMIZATION WITH REORDERING OF GENETIC TEST VECTORS FOR VLSI CIRCUITS. Singh, Balwinder; Narang, Sukhleen Bindra; Khosla, Arun // Acta Technica Napocensis. Electronica-Telecomunicatii;2012, Vol. 53 Issue 2, p1 

    Power optimization is one of the important challenges in VLSI circuit for testing engineers. Larger power dissipation becomes the reason for overheating and with every increase in 10°C in operating temperature, failure rates for the component on a chip doubles. Power dissipation is directly...


Read the Article


Sorry, but this item is not currently available from your library.

Try another library?
Sign out of this library

Other Topics