TITLE

Network processors get new tools

AUTHOR(S)
Cravotta, Nicholas
PUB. DATE
March 2001
SOURCE
EDN;03/15/2001, Vol. 46 Issue 6, p22
SOURCE TYPE
Trade Publication
DOC. TYPE
Article
ABSTRACT
Focuses on IBM Corp. and Intel's enhancement of the tool suites for their network processors. Linux-based suite from IBM Corp.; Support for the PowerNP NP4GS3 network processor; Microengine C compiler from Intel; Volume pricing for the IXP1200 network-processor line.
ACCESSION #
4238467

 

Related Articles

  • PATHSCALE EKO COMPILER SUITE ADOPTION ACCELERATES.  // UNIX Update;Nov2004, Vol. 15 Issue 11, p5 

    This article focuses on the PathScale EKO Compiler Suite of PathScale, a developer of the world's fastest compilers for AMD(R) Opteron processor-based Linux clusters. Many of the highest-profile research and development organizations in North America, Europe and Asia have adopted AMD Opteron...

  • Cores lower entry cost for custom SOCs. Cravotta, Robert // EDN;3/16/2006, Vol. 51 Issue 6, p22 

    The article provides information on the Diamond Standard family of processor configurations of Tensilica which is based on the Xtensa architecture. Each core implements the Xtensa instruction-set architecture in a five-stage pipeline, 32-bit architecture. The family consists the 108Mini, a...

  • Visual Studio .net at risk of buffer overflow attack. Doyle, Eric // Computer Weekly;2/21/2002, p2 

    Focuses on the vulnerability of the C++ compiler used in Visual Studio.net in Great Britain. Susceptibility of the executable code to buffer overflow attacks; Failure of the protection mechanism to eliminate buffer overflows; Statement of Stuart Okin, chief security officer of Microsoft on the...

  • Scalarization Using Loop Alignment and Loop Skewing. Zhao, Yuan; Kennedy, Ken // Journal of Supercomputing;Jan2005, Vol. 31 Issue 1, p5 

    Array syntax, which is supported in many technical programming languages, adds expressive power by allowing operations on and assignments to whole arrays and array sections. To compile an array assignment statement to a uniprocessor, the language processor must convert the statement into a loop...

  • Interfacing C and TMS320C6713 Assembly Language (Part-I). Wardak, Abdullah A. // Proceedings of World Academy of Science: Engineering & Technolog; 

    This paper describes an interfacing of C and the TMS320C6713 assembly language which is crucially important for many real-time applications. Similarly, interfacing of C with the assembly language of a conventional microprocessor such as MC68000 is presented for comparison. However, it should be...

  • Data Cache Prefetching With Dynamic Adaptation. Khan, Minhaj Ahmad // Computer Journal;May2011, Vol. 54 Issue 5, p815 

    Modern processors based on VLIW architecture rely heavily on software cache prefetching incorporated by the compiler. For accurate prefetching different factors such as latencies of the loop iterations need to be taken into account, which cannot be determined at (static) compile time....

  • Inside the Intel 10.1 Compilers: New Threadizer and New Vectorizer for Intel Core2 Processors. Xinmin Tian; Su, Ernesto; Kreitzer, David; Saito, Hideki; Krishnaiyer, Rakesh; Kanhere, Abhay; Ng, John; Chu-Cheow Lim; Ghosh, Somnath // Intel Technology Journal;Nov2007, Vol. 11 Issue 4, p263 

    The fast introduction of the Intel® Core™2 Duo and Quad processors to the mass market has drawn attention to threadization (a.k.a. parallelization) and vectorization of the existing code in many application domains. In fact, multi-core processor vendors are eager to enable their users...

  • Multi-Core Processors Offer Significant Gains. Stahl, Earl // Database Trends & Applications;Aug2007, Vol. 21 Issue 8, p10 

    The article presents an opinion regarding the benefits that high performance multi-core processors provide in terms of compiler performance and computer software development. Simultaneous multithreading processors can be used by software vendors to deliver enhanced features for software that...

  • Compiler-Aided Run-Time Performance Speed-Up in Super-Scalar Processor. Pelleh, Mosche // Issues in Informing Science & Information Technology;2009, Vol. 6, p837 

    In our world, where most systems become embedded systems, the approach of designing embedded systems is still frequently similar to the approach of designing organic systems (or not embedded systems). An organic system, like a personal computer or a work station, must be able to run any task...

Share

Read the Article

Courtesy of THE LIBRARY OF VIRGINIA

Sorry, but this item is not currently available from your library.

Try another library?
Sign out of this library

Other Topics