Improvement of subthreshold swing of n-channel transistor by uniaxial tensile stress due to a quantum mechanical mechanism instead of physical thinning

Lau, W. S.; Yang, Peizhen; Lai, Seow Wei; Lo, V. L.; Siah, S. Y.; Chan, L.
April 2009
Applied Physics Letters;4/27/2009, Vol. 94 Issue 17, p173503
Academic Journal
Physical thinning of the gate dielectric due to uniaxial tensile stress is expected to improve the subthreshold swing (Sts) of both n-channel and p-channel metal-oxide-semiconductor (MOS) transistors. However, experimentally, we observed a small improvement in Sts of n-channel MOS transistors but a small degradation in Sts of p-channel MOS transistors due to the application of uniaxial tensile stress. Uniaxial tensile stress modifies the out-of-plane effective mass of electrons or holes, resulting in a change in Sts, which can be predicted by quantum mechanics.


Related Articles

  • Quasi-conformal transformation optics with elasto-electromagnetic metamaterials: Design algorithm. Dongheok Shin; Junhyun Kim; Ilsung Seo; Kyoungsik Kim // Applied Physics Letters;7/13/2015, Vol. 107 Issue 2, p021908-1 

    We report here a design method that is used to determine the initial shapes of elastoelectromagnetic metamaterial blocks with respect to the given shape of a hiding object when these blocks are applied to the problem of carpet cloaking. Starting from the inhomogeneous permittivity distribution...

  • Simulation Based Multifunctional MOS Device by Externally Controlled Gate Width. Gopi, B.; Wahida Banu, R. S. D. // European Journal of Scientific Research;8/9/2011, Vol. 57 Issue 3, p426 

    The world's demand for high-speed devices and equipments are growing very drastically. Every individual researcher in all country is marching towards, to achieve it .The role of Design Engineer has become very important to cater the above needs. As per Moor' law packing density doubles every...

  • Enhanced Leakage Control in Scaled 45nm nMOS Devices using SiO2 and Si3N4. Dhar, Subhra; Pattanaik, Manisha; Rajaram, P. // International Journal of Computer Applications;Sep2011, Vol. 29, p5 

    Gate-leakage reduction is the key motivation for the replacement of SiO2 with alternative gate dielectrics. 45nm gate length scaled grooved and bulk nMOSFETs are evaluated to bring out the most compatible and power saving dielectric option using Si3N4 and SiO2 using Silvaco ATLAS device...

  • Electrical and structural properties of high-k Er-silicate gate dielectric formed by interfacial reaction between Er and SiO2 films. Choi, Chel-Jong; Jang, Moon-Gyu; Kim, Yark-Yeon; Jun, Myung-Sim; Kim, Tae-Youb; Song, Myeong-Ho // Applied Physics Letters;7/2/2007, Vol. 91 Issue 1, p012903 

    The authors investigate the electrical and structural properties of high-k Er-silicate film formed by the interfacial reaction between Er and SiO2 films. The increase in rapid thermal annealing temperature leads to the reduction of the interface trap density by one order of magnitude, indicating...

  • LaAlO3 gate dielectric with ultrathin equivalent oxide thickness and ultralow leakage current directly deposited on Si substrate. Suzuki, Masamichi; Yamaguchi, Takeshi; Fukushima, Noburu; Koyama, Masato // Journal of Applied Physics;Feb2008, Vol. 103 Issue 3, p034118 

    By a careful choice of film deposition conditions, LaAlO3 (LAO) gate dielectric film with equivalent oxide thickness (EOT) of 0.31 nm and gate leakage current density (Jg) of 0.1 A/cm2 (at Vfb+1 V) has been successfully demonstrated. Elimination of interfacial low-k layer at LAO/Si and reduction...

  • Power-Area trade-off for Different CMOS Design Technologies. Priyadarshini. V.; G. R. L. V. N. Srinivasa Raju // International Journal of Computer Technology & Applications;Jul-Aug2012, Vol. 3 Issue 4, p1388 

    With the advancement of technology, Integrated Chip (IC) has achieved smaller chip size with more functions integrated. Through the usage of more transistors, it has lead to an increase of power dissipation and undesired noise. As the design gets more complex, this results in slower speed....

  • Design of Low Power CMOS Circuits using Leakage Control Transistor and Multi-Threshold CMOS Techniques. U. Supriya; K. Ramana Rao // International Journal of Computer Technology & Applications;Jul-Aug2012, Vol. 3 Issue 4, p1496 

    The scaling down of technology in CMOS circuits, results in the down scaling of threshold voltage thereby increasing the sub-threshold leakage current. An IC consists of many circuits of which some circuits consists critical path like full adder, whereas some circuits like multiplexer and...

  • Controlling interfacial reactions between HfO2 and Si using s Al2O3 diffusion barrier layer. Katamreddy, Rajesh; Inman, Ronald; Jursich, Gregory; Soulet, Axel; Takoudis, Christos // Applied Physics Letters;12/25/2006, Vol. 89 Issue 26, p262906 

    The authors investigated the effectiveness of atomic layer deposited (ALD) aluminum oxide barrier layer in controlling the interfacial reaction between ALD HfO2 film and Si substrate. The HfO2 was observed to form silicate and silicide at its interface with Si during 5 min postdeposition...

  • A Novice Approach of Designing CMOS Based Switchable Filters for ASP Applications. Tiwari, Rajinder; Mishra, G. R. // International Journal of Electrical & Computer Engineering (2088;Dec2015, Vol. 5 Issue 6, p1354 

    A switchable filter can be designed and fabricated with the desired range and parameters, materials say quartz substrate for RF MEMS based applications. The mathematical modeling of the resonators using the desired characteristics of the capacitive coupled filters can be implemented with low...


Read the Article


Sorry, but this item is not currently available from your library.

Try another library?
Sign out of this library

Other Topics