TITLE

High bandwidth force estimation for optical tweezers

AUTHOR(S)
Sehgal, Hullas; Aggarwal, Tanuj; Salapaka, Murti V.
PUB. DATE
April 2009
SOURCE
Applied Physics Letters;4/13/2009, Vol. 94 Issue 15, p153114
SOURCE TYPE
Academic Journal
DOC. TYPE
Article
ABSTRACT
A prevalent mode of optical tweezers involves position clamping that regulates a constant position of a trapped bead. Traditional schemes employ the measured bead position in the open loop or the control signal in the position-clamp mode as an estimate of external force on the trapped bead. This article shows that traditional methods introduce fundamental limitations on bandwidth of the external force estimation. A method is presented that leads to an order of magnitude increase in the bandwidth of the external force estimation. Furthermore, a comprehensive modeling paradigm is introduced that facilitates estimation of forces on the bead.
ACCESSION #
37831796

 

Related Articles

  • A Novel Design Technique to Speed-Up the Charge Pump and Improve the Stability of PLLs. Karimi, Gh. R.; Atani, R. E.; Beighi, A. Taleb // International Review on Computers & Software;Nov2010, Vol. 5 Issue 6, p671 

    In this paper, a novel technique for increasing the stability of integer-N CMOS Phase Locked Loops (PLLs) is presented. The method is based on the change of load capacitance which improves the stability of the second order PLL. Indeed, when PLL is in transient state and system is locked to...

  • DESIGN AND IMPLEMENTATION OF A NOVEL FREQUENCY MODULATION CIRCUIT USING A PHASE-LOCKED LOOP SYNTHESIZER. Seong-Sik Yang; Jong-Hwan Lee; Kyung-Whan Yeom // Microwave Journal;Feb2005, Vol. 48 Issue 2, p80 

    A phase-locked loop (PLL) is widely used in frequency .synthesizers for modem communication systems. However, frequency modulation (FM) of a PLL for the modulation rates used inside the loop bandwidth, is generally difficult. In this article, a novel hut simple FM circuit of a PLL is described,...

  • Select A VCO or YIG For A PLL Synthesizer? CHENAKIN, ALEXANDER // Microwaves & RF;Apr2011, Vol. 50 Issue 4, p25 

    The article reports that performance phase-lock-loop (PLL) frequency synthesizers rely on yttrium-iron-garnet (YIG) oscillators featuring broadband operation and excellent phase noise. It is stated that YIG-tuned oscillators also offer very linear and repeatable tuning characteristics that...

  • Experimental Investigation of Low-Jitter and Wide-Band Dual Cascaded PLL System. Telba, Ahmed; Qasim, Syed Manzoor // AIP Conference Proceedings;8/25/2011, Vol. 1373 Issue 1, p59 

    Jitter is a matter of great concern for high-speed digital designers because of its ability to degrade the overall system performance. Designing a low-jitter and wide-band phase locked loop (PLL) system is of practical importance because of its application in high speed digital systems. This...

  • Carrier Synchronization in Software Defined Radio using Costas Loop. Priya, A.; Rajesh, N.; Muthaiah, R. // Indian Journal of Science & Technology;Jun2013, Vol. 6 Issue 6, p4697 

    This paper presents carrier synchronization in software defined radio for 8PSK technique. Software Defined Radio (SDR) plays a major solution for the need for flexibility, upgradability, and the problems of implementing multiple radio standards alternatively and even running several services in...

  • Auction-Based Effective Bandwidth Allocation Mechanism. Eiji Takahashi; Yoshiaki Tanaka // Telecommunication Systems;Oct2003, Vol. 24 Issue 2, p323 

    Several auctions have been proposed and applied to perform contract negotiation and resource allocation in reservation-based networks. The methods proposed by these works perceive resources as single items with multiple units and place importance on a limited efficiency inside each node....

  • Internet connection speeds: dial-up and broadband. Hern├índez, Gina M. // Caribbean Business;9/16/2010, Vol. 38 Issue 36, p23 

    The article focuses on the various connection speeds used by residents, with broadband Internet on their homes, in Puerto Rico. According to the Network Readiness Index, the island is in the 45th place in terms of business access to broadband. It also cites the continuous increase of Internet...

  • Jitter peaking and PLLs. Giust, Gary // EDN;9/13/2007, Vol. 52 Issue 19, p24 

    The article describes the problem of electronic signal degradation when engineers are creating clock trees by cascading three identical phase-locked-loop (PLL). The problem called jitter peaking can cause instability or timing failures, as well as affect a system's performance. To avoid using...

  • VCO Presteering for PLL Gain Compensation. Alechno, Stan // Wireless Design & Development;Apr2004, Vol. 12 Issue 4, p30 

    Reveals that when designing broadband frequency synthesis circuits with Phase Locked Loop, an essential problem arises, which is the variation of the open loop transmittance. Equation for the transfer function; Description of the method developed for compensating the open loop gain variations;...

Share

Read the Article

Courtesy of THE LIBRARY OF VIRGINIA

Sorry, but this item is not currently available from your library.

Try another library?
Sign out of this library

Other Topics