One Bit to Rule Them All

Gomes, Lee
December 2008
Forbes Asia;12/8/2008, Vol. 4 Issue 21, p88
The article provides information on memory devices. It states that the first memory devices were created in the 1950s called core memories which require various intersecting wires, and ceramic ring. In the present days, the silicon chips applied in the most vital applications, such as the high speed random access memory, had become so dense. It also mentions that the merged global industries of disk storage and semiconductor memory are more or less $90 billion worth per year.


Related Articles

  • Non-volatile DRAM sets stage for new system design.  // Design News;3/25/91, Vol. 47 Issue 6, p28 

    Reports that the FMx 1208 from Ramtron Corp. is semiconductor memory that combines read/write performance, the endurance of dynamic random access memory (DRAM) technology, and the nonvolatility of the magnetic disk. Based on ferroelectric DRAM; Merging ferroelectric materials with integrated...

  • Toshiba Unveils Logical Block Addressing NAND.  // Electronic News;8/7/2006, Vol. 52 Issue 32, p50 

    The article reports on the logical block addressing brought by Toshiba Corp. to NAND flash memory in an effort to speed time to market, simplify design and eliminate the need for the host to handle NAND management functions. Toshiba said the new technology is ideal for consumer devices such as...

  • DRAM, NAND woes seen spilling into 2009.  // Solid State Technology;Oct2008, Vol. 51 Issue 10, p14 

    The article reports on the findings of the study by iSuppli Corp. regarding the performance of the dynamic random access memory (DRAM) and the Not AND (NAND) markets. According to iSuppli, global DRAM manufacturers are again building inventories despite a milk recovery in the second quarter of...

  • A flash of magic NAND. Manners, David // Electronics Weekly;5/7/2003, Issue 2098, p22 

    Highlights the transformation of the flash memory technology from its root in the NOR random access memory into the NAND serial access memory for data storage. Market share of NAND memory in the memory technology market; License agreement of Toshiba with Samsung Electronics Co. for NAND memory...

  • Lifetime-aware capacity dynamic adjusting for Solid state disk. Kai Bu; Haijun Liu; Hui Xu; Zhaolin Sun // Applied Mechanics & Materials;2014, Issue 513-517, p3630 

    In this paper, we analyzed the endurance of Nand Flash memory and then proposed a level adjusting scheme to use the MLC Flash dynamically to storage different amount of data levels through the entire lifetime. The result shows that the MLC SSD adopting this method could be totally written 4.8X...

  • Switching dynamics and charge transport studies of resistive random access memory devices. Long, Branden; Li, Yibo; Mandal, Saptarshi; Jha, Rashmi; Leedy, Kevin // Applied Physics Letters;9/10/2012, Vol. 101 Issue 11, p113503 

    We report the switching dynamics and charge transport studies on Ru/HfO2/TiOx/Ru resistive random access memory devices in low resistance state (LRS), high resistance state (HRS), and virgin resistance state (VRS). The charge transport in LRS is governed by Ohmic conduction of electrons through...

  • Uniform Ti-doped Sb2Te3 materials for high-speed phase change memory applications. Min Zhu; Liangcai Wu; Feng Rao; Zhitang Song; Kun Ren; Xinglong Ji; Sannian Song; Dongning Yao; Songlin Feng // Applied Physics Letters;2/3/2014, Vol. 104 Issue 5, p053119-1 

    Compared with pure Sb2Te3, Ti0.32Sb2Te3 (TST) phase change material has larger resistance ratio, higher crystallization temperature and better thermal stability. The sharp decrease in mobility is responsible for the increasing amorphous and crystalline sheet resistance. The uniform crystalline...

  • Random Telegraph Noise modulation by switching bias in Floating Gate memory devices. Fantini, Paolo; Calderoni, Alessandro; Marinoni, Andrea // AIP Conference Proceedings;2007, Vol. 922 Issue 1, p119 

    Aim of the present work is to investigate the Random telegraph Signal (RTS) in a Floating Gate based memory cell (Flash memory) when the device is rapidly and periodically turned “on” and “off”. In particular, the low-frequency noise dependence as a function of frequency...

  • A BICS Design to Detect Soft Error in CMOS SRAM. Sivamangai, N. M.; Gunavathi, K.; Balakrishnan, P. // International Journal on Computer Science & Engineering;2010, Vol. 2 Issue 3, p734 

    This paper presents a Built In Current Sensor (BICS) design to detect soft error under both standby and operating condition in Complementary Metal Oxide Semiconductor (CMOS) Static Random Access Memory (SRAM). BICS connected in each column of SRAM cell array detects various values of current...


Read the Article


Sorry, but this item is not currently available from your library.

Try another library?
Sign out of this library

Other Topics