TITLE

Integration of vertical InAs nanowire arrays on insulator-on-silicon for electrical isolation

AUTHOR(S)
Dayeh, Shadi A.; Peng Chen; Yi Jing; Yu, Edward T.; Lau, S. S.; Deli Wang
PUB. DATE
November 2008
SOURCE
Applied Physics Letters;11/17/2008, Vol. 93 Issue 20, p203109
SOURCE TYPE
Academic Journal
DOC. TYPE
Article
ABSTRACT
Vertical and electrically isolated InAs nanowires (NWs) are integrated with Si in a technique that bypasses structural defects and transport barriers at the Si–III–V NW interface. Smart-cut® technique is used to transfer a thin InAs layer onto SiO2/Si and is subsequently used for ordered organometallic vapor phase epitaxy of InAs NWs. The InAs layer in the regions between the InAs NWs is etched resulting in ordered, vertical, and electrically isolated InAs NW arrays. This transfer and fabrication technique enables heteroepitaxy of three dimensional III–V structures on Si and allows the realization of vertical devices with unprecedented control over their architectures.
ACCESSION #
35514084

 

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