TITLE

Mentor Graphics Announces an Optimized FPGA Design Flow

PUB. DATE
December 2007
SOURCE
Portable Design;Dec2007, Vol. 13 Issue 12, p8
SOURCE TYPE
Periodical
DOC. TYPE
Article
ABSTRACT
The article reports on the installation of a hardware description language (HDL) by MathWorks Inc. Simulink HDL Code into the Mentor Graphics Precision suite of advanced synthesis products of Mentor Graphics Corp. in the U.S. The new addition enables mutual customers to generate an optimized netlist implementation for field programmable gate array designs (FPGA). It also targets to improve the productivity of FPGA design synthesis, as well as to ensure its interoperability.
ACCESSION #
34943470

 

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