Mentor Graphics Announces an Optimized FPGA Design Flow

December 2007
Portable Design;Dec2007, Vol. 13 Issue 12, p8
The article reports on the installation of a hardware description language (HDL) by MathWorks Inc. Simulink HDL Code into the Mentor Graphics Precision suite of advanced synthesis products of Mentor Graphics Corp. in the U.S. The new addition enables mutual customers to generate an optimized netlist implementation for field programmable gate array designs (FPGA). It also targets to improve the productivity of FPGA design synthesis, as well as to ensure its interoperability.


Related Articles

  • FPGA tool flow synthesises designs from Simulink.  // EDN Europe;Jan2008, Vol. 53 Issue 1, p51 

    The article evaluates the field-programmable gate array system from the MathWorks Inc. and Mentor Graphics.

  • Mentor Graphics develops complete FPGA design flow.  // Electronics Weekly;5/28/2003, Issue 2101, p6 

    Reports on the development of a field programmable gate array (FPGA) design flow by Mentor Graphics in May 2003. Forms of design entry; Change in the FPGA synthesis tool used by Mentor; Efforts done to maintain the design productivity advantage of FPGA.

  • Take me higher. Wilson, Richard // Electronics Weekly;6/4/2003, Issue 2102, p23 

    Looks at several high-level system-on-chip synthesis tools designed to synthesize field programmable gate arrays. Information on Simplicity's Multipoint synthesis tool; Details on the HDL Designer Series of Mentor Graphics; Capabilities of the Hardware Design System.

  • Mentor Tool Links PCB, FPGA.  // Printed Circuit Design & Manufacture;Sep2004, Vol. 21 Issue 9, p8 

    Reports on the release of I/O Designer, a tool that facilitates concurrent chip-to-board design of field programmable gate arrays and printed-circuit boards developed by Mentor Graphics Corp. Symbols provided by I/O Designer's automated schematic symbol generation function; Comments from John...

  • FPGA or EDA? Sperling, Ed // Electronic News;12/8/2003, Vol. 49 Issue 49, pN.PAG 

    Reports on the plan of Mentor Graphics to launch a physical synthesis tool for the field programmable gate array (FPGA) market. Impact of the plan on low-cost FPGA tools produced by FPGA vendors and those made by electronic design automation companies; Statement from Tim Southgate, VP of...

  • Shorten FPGA-integration time in pc-board design. Moretti, Gabe // EDN;9/18/2003, Vol. 48 Issue 20, p22 

    Introduces the field programmable gate array BoardLink from Mentor Graphics. Advantages of using BoardLink in designing printed circuit boards; Other tools integrated with the BoardLink.

  • Tool tackles complex FPGAs. Moretti, Gabe; Granville, Fran // EDN;2/5/2004, Vol. 49 Issue 3, p18 

    Evaluates the Precision Physical Synthesis field programmable gate array (FPGA) tool from Mentor Graphics. Use of FPGA as alternative to application specific integrated circuits; Product design features; Operational specifications.

  • Counting on gate counts? Don't count on it. Dipert, Brian // EDN;08/03/98, Vol. 43 Issue 16, p52 

    Offers advice which can by utiliuzed when selecting complex- programmable logic device (CPLDs) and field programmable gate arrays (FPGAs). Use of a programmable AND and fixed OR architecture by CPLDs; Advantages of CPLDs and FPGAs; Reference to the QuickLogic which offers the free Web-based...

  • Careful HDL coding maximizes performance in LUT-based FPGAs. Samhouri, Samir // Electronic Design;12/14/98, Vol. 46 Issue 28, p51 

    Discusses the importance of understanding the interaction between HDL coding style, field-programmable gate array (FPGA) device architectures and design software in maximizing lookup tables (LUT)-based FPGAs. FPGA features that synthesis tools may have difficulty implementing; Configuration of...


Read the Article


Sorry, but this item is not currently available from your library.

Try another library?
Sign out of this library

Other Topics