Synopsys donates VMM methodology library, apps to standards group

Mutschler, Ann Steffora
May 2008
Electronic News;5/19/2008, Vol. 54 Issue 20, p3
Trade Publication
The article informs that the semiconductor design and manufacturing software company Synopsys Inc. has given its SystemVerilog verification methodology into standards group Accellera for use in developing verification standards. To support verification interoperability standardization in the semiconductor design industry, Synopsys Inc. has reported that it is donating its complete implementation of the Verification Methodology Manual (VMM) to standards organization Accellera.


Related Articles

  • VMM application packages: the next level of productivity. Bergeron, Janick // EDN;2/21/2008, Vol. 53 Issue 4, p49 

    The article provides information on the "Verification Methodology Manual" (VMM) which documents advanced functional verification techniques used by industry experts to validate complex system-on-chip (SoC). Unlike verification environments, VMM application packages are useful in implementing a...

  • ARM, Synopsys bid to shape IP verification with "how-to" manual. Butler, Maura // EDN Europe;Mar2004, Vol. 49 Issue 3, p18 

    Reports on Synopsys' plan to introduce in collaboration with ARM, a draft text of the how-to guide "Verification Methodology Manual". Goal for the move; Significance of the collaboration to both companies.

  • ACCELLERA/SPIRIT WIN TENZING NORGAY AWARD.  // Electro Manufacturing;Sep2009, Vol. 22 Issue 9, p2 

    The article announces that Accellera Organization Inc. and The SPIRIT Consortium have been presented an award at the ninth annual Tenzing Norgay Interoperability Achievement Award of Synopsys Inc. in the U.S.

  • DAC: System Verilog Mired in Politics. Sperling, Ed // Electronic News;6/14/2004, Vol. 50 Issue 24, pN.PAG 

    Comments on the committee process at Accellera. Acquisition of Co-Design Automation by Synopsys; Support of Cadence Design Systems and Verisity on System C language; Benefits from System Verilog; Performance of the System C.

  • Design and Realization of Efficient Verification Platform Based on System Verilog. Meihua Xu; Qin Yu; Aiying Guo // Advanced Materials Research;2014, Vol. 945-949, p1903 

    Adopting the Verification Methodology Manual's (VMM) hierarchical structure, this paper presents a design of available verification platform based on System Verilog adopted. The platform completed can implement constrained-random test, directed test, and error stimulus test with high efficiency;...

  • Synopsys revamps IC Complier with multi-threaded routing technology. Mutschler, Ann Steffora // Electronic News (10616624);6/2/2008, Vol. 54 Issue 22, p3 

    The article reports that Mountain View, California-based semiconductor design and manufacturing software supplier Synopsys Inc. has rolled out Zroute, a new multi-threaded router. The router is completely integrated into the company's IC Compiler physical design software. Synopsys said the...

  • Design Compiler 2010 steps up synthesis productivity. Prophet, Graham // EDN Europe;Apr2010, Vol. 57 Issue 4, p15 

    The article offers brief information on the Design Compiler 2010 tool set for semiconductor design from Synopsys Inc.

  • SYSTEM VERILOG Gains A Foothold In Verification. Maliniak, David // Electronic Design;5/25/2006, Vol. 54 Issue 11, p49 

    The article focuses on System Verilog, a design/verification language by Accellera's System Verilog Working Group. System Verilog combines a number of verification concepts. This is mainly in the areas of assertions, design and testbench creation. For partitioning, System Verilog can be divided...

  • Accellera Board Approves New Version of Analog, Mixed-Signal Standard.  // Portable Design;Sep2008, Vol. 14 Issue 9, p7 

    The article evaluates the Verilog-Analog Mixed-Signal (AMS) standard version from Accellera Organization Inc.


Read the Article


Sorry, but this item is not currently available from your library.

Try another library?
Sign out of this library

Other Topics