Dual-thread Speculation: A Simple Approach to Uncover Thread-level Parallelism on a Simultaneous Multithreaded Processor

Warg, Fredrik; Stenstrom, Per
April 2008
International Journal of Parallel Programming;Apr2008, Vol. 36 Issue 2, p166
Academic Journal
As chip multiprocessors with simultaneous multithreaded cores are becoming commonplace, there is a need for simple approaches to exploit thread-level parallelism. In this paper, we consider thread-level speculation as a means to reap thread-level parallelism out of application binaries. We first investigate the tradeoffs between scheduling speculative threads on the same core and on different cores. While threads contend for the same resources using the former approach, the latter approach is plagued by the overhead for inter-core communication. Despite the impact of resource contention, our detailed simulations show that the first approach provides the best performance due to lower inter-thread communication cost. The key contribution of the paper is the proposed design and evaluation of the dual-thread speculation system. This design point has very low complexity and reaps most of the gains of a system.


Related Articles

  • A Case for Chip Multiprocessors Based on the Data-Driven Multithreading Model. Trancoso, Pedro; Evripidou, Paraskevas; Stavrou, Kyriakos; Kyriacou, Costas // International Journal of Parallel Programming;Jun2006, Vol. 34 Issue 3, p213 

    Current high-end microprocessors achieve high performance as a result of adding more features and therefore increasing complexity. This paper makes the case for a Chip-Multiprocessor based on the Data-Driven Multithreading (DDM-CMP) execution model in order to overcome the limitations of current...

  • The Impact of Speculative Execution on SMT Processors. Kang, Dongsoo; Liu, Chen; Gaudiot, Jean-Luc // International Journal of Parallel Programming;Aug2008, Vol. 36 Issue 4, p361 

    By executing two or more threads concurrently, Simultaneous MultiThreading (SMT) architectures are able to exploit both Instruction-Level Parallelism (ILP) and Thread-Level Parallelism (TLP) from the increased number of in-flight instructions that are fetched from multiple threads. However, due...

  • Synchronous cooperation for explicit multi-threading. Bergstra, J.; Middelburg, C. // Acta Informatica;Dec2007, Vol. 44 Issue 7/8, p525 

    We develop an algebraic theory of threads, synchronous cooperation of threads and interaction of threads with Maurer machines, and investigate program parallelization using the resulting theory. Program parallelization underlies techniques for speeding up instruction processing on a computer...

  • Hardware Support for Fine-Grain Multi-Threading in LEON3. Danˇek, M.; Kafka, L.; Kohout, L.; S´ykora, J. // Carpathian Journal of Electronic & Computer Engineering;2011, Vol. 4 Issue 1, p27 

    The article describes instruction set extensions for a variant of multi-threading called micro-threading for the LEON3 SPARCv8 processor. An architecture of the developed processor ispresented and its key blocks described - cache controller, register file, thread scheduler. The processor has...

  • On Exploiting Heterogeneity for Cluster Based Parallel Multithreading Using Task Duplication. Kwok, Yu-Kwong // Journal of Supercomputing;May2003, Vol. 25 Issue 1, p63 

    Triggered by the ever increasing advancements in processor and networking technology, a cluster of PCs connected by a high-speed network has become a viable and cost-effective platform for the execution of computation intensive parallel multithreaded applications. However, there are two research...

  • The exception handler of multithreaded processors. Jih-fu, T. U. // Journal of Communication & Computer;Mar2007, Vol. 4 Issue 3, p1 

    Threading is one of the effective schemes to improve the performance of processors. This paper uses the threading scheme to implement a multithreaded processor, which is the combination of several thread slots (also called thread processing unit) and Thread Communication Unit (TCU). The thread...

  • MIPS chip signals debut in parallel processing. Bush, Steve // Electronics Weekly;4/2/2008, Issue 2329, p1 

    The article reports that MIPS Technologies Inc. has unveiled its first parallel processing core 1004k. According to Jack Browne, MIPS's vice-president marketing, it is their first multi-processor multi-threading core. The processor is similar to the firm's existing 34k midrange central...

  • Memory Access Dependencies in Shared-Memory Multiprocessors. Dubois, Michel; Scheurich, Christoph // IEEE Transactions on Software Engineering;Jun90, Vol. 16 Issue 6, p660 

    A multiprocessor system designed to support multithreading must adhere to a simple logical model of concurrency. Besides executing each process correctly; the multiprocessor must preserve the dependencies among processes. Dependencies among concurrent processes are specified by explicit...

  • Multi-CPU architecture speeds ray tracing. Gauvin, Michael; Scott, Donald // Laser Focus World;Mar2007, Vol. 43 Issue 3, p49 

    The article focuses on the importance of multithreading technology in computers. The innovation refers to the merging of several computers onto a single chip to provide the equivalent of multiple computer capability on the desktop. According to the author, this technology have been very useful...


Read the Article


Sorry, but this item is not currently available from your library.

Try another library?
Sign out of this library

Other Topics