TITLE

Wet lithography gives TI edge on 45mm process

AUTHOR(S)
Wilson, Richard
PUB. DATE
June 2006
SOURCE
Electronics Weekly;6/21/2006, Issue 2246, p17
SOURCE TYPE
Trade Publication
DOC. TYPE
Article
ABSTRACT
This article reports that Texas Instruments Inc. will double the number of chips produced on each silicon wafer. Presenting details of its 45nm process at last week's symposium on VLSI Technology, the firm also said the process, based on so-called 'wet' lithography, would increase performance of its DSP devices by 30 percent while reducing power consumption 40 percent. In practice, the processing performance increase achievable with this next generation chip fabrication will translate into higher quality video on mobile phones and greater potential for terminals to run simultaneous applications.
ACCESSION #
21604708

 

Related Articles

  • Land Of The Rising Sun -- And Technologies -- Hosts VLSI Symposia. Bursky, Dave // Electronic Design;5/12/2005, Vol. 53 Issue 10, p25 

    The article reports that the IEEE 2005 Symposium on VLSI technology will celebrate its 25th anniversary from June 14-16 in Kyoto, Japan. This conference will highlight cutting edge CMOS front-end to back-end processes that use features as small as 32nm. Attendees also can learn about the latest...

  • Test Technology Newsletter.  // Journal of Electronic Testing;Oct2012, Vol. 28 Issue 5, p553 

    A calendar of events related to test technology in 2012 is presented which includes the 17th East-West Design & Test Symposium (EWDTS) 2012 in Ukraine, the 8th IEEE International Workshop in California, and the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology...

  • Integration paces point-tool development. Nelson, Rick // Test & Measurement World;Jun2006, Vol. 26 Issue 5, p17 

    The article highlights the 2006 VLSI Test Symposium held on May 1, 2006 in Berkeley, California. The symposium explored the future of design for test (DFT). The main question was whether point tools or integrated DFT environments are best. Representatives from several companies including Cadence...

  • Overlay Metrology in VLSI Design for Manufacturability. Li Jiang; Chung Han Chen; Naga S. Korivi // International Journal on Recent Trends in Engineering & Technolo;Nov2010, Vol. 4 Issue 4, p128 

    Overlay metrology refers to the measurement of relative feature position from one photolithographic level to another in the manufacturing process for semiconductor devices and integrated circuits. Overlay measurement yields information about alignment accuracy, lithographic tool performance, and...

  • Using Multiple Implant Regions To Reduce Development Wafer Usage. Walther, S. R.; Falk, S.; Mehta, S.; Erokhin, Y.; Nunan, P. // AIP Conference Proceedings;2006, Vol. 866 Issue 1, p409 

    The cost of new process development has risen significantly with larger wafer sizes and the increased number of fabrication steps needed to create advanced devices. The high value of each 300 mm development wafer has spurred efforts to find a way to explore more than a single process setting...

  • Simulation and Implemention of Speech Compression Algorithms in VLSI. B. Karthik; Kumar, T. V. U. Kiran; M. Sundar Raj; Kumaran, E. Bharath // Middle East Journal of Scientific Research;9/22/2013, Vol. 15 Issue 12, p1745 

    The rapid growth of the enhancement of the capacity of wireless networks has triggered a need for data compression applicable to speech and image. This project mainly aims at the development of efficient speech compression algorithms based on ADPCM, Huffman coding, run length coding. ADPCM...

  • Summarization of Intra/Inter Chip Wireless Interconnection Technology. WANG Yi-wen; LI Xue-hua // Telecommunication Engineering;Jul2014, Vol. 54 Issue 7, p1031 

    To solve the complex wiring problem of very large scale integrated circuit(VLSI),wireless interconnection technology(WIT) emerges as the times require. This paper introduces two techniques to realize intra / inter chip wireless interconnection, namely wireless interconnection technique based on...

  • Wireless Cellular Communication Using 100 Nanometers Spintronics Device Based VLSI. Thooyamani, K. P.; Khanaa, V.; Udayakumar, R. // Middle East Journal of Scientific Research;2/23/2014, Vol. 20 Issue 12, p2037 

    Rapid progress in the miniaturization of the semiconductor electronic devices leads towards chip features smaller than 100 nanometers in size. This revolution offers opportunities for developing a new generation of device incorporating standard microelectronics with spin-dependent effects...

  • Low Power Blind Adaptive Equalizer with Word Length Optimization Algorithm. Manga, N. Alivelu; Latha, M. Madhavi // International Journal of Computer Applications;Aug2014, Vol. 100, p55 

    Low power VLSI is a promising area for developing advanced wireless communication systems. The optimum word length selection for each signal in algorithm is crucial for low power design. This paper proposes a scheme for Word Length Optimization (WLO) using system level parameters such as dynamic...

Share

Read the Article

Courtesy of VIRGINIA BEACH PUBLIC LIBRARY AND SYSTEM

Sorry, but this item is not currently available from your library.

Try another library?
Sign out of this library

Other Topics