Zenasis adds tool for 'no back end' teams

March 2006
Electronics Weekly;3/29/2006, Issue 2234, p18
Trade Publication
This article reports that U.S. EDA firm Zenasis Technologies Inc. has added a product to its line of tools for automated standard cell optimisation. ZenTime-GT performs gate-level analysis of critical paths to improve timing, and can be used to enhance device performance without shifting to smaller process geometries. Zenasis's tools use techniques such as buffer insertion; continuous gate sizing for discrete drive strengths; pin permutation; and inverted logic gates to enable optimisation for leakage power, timing and area.


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