Process development and bonding quality investigations of silicon layer stacking based on copper wafer bonding

Chen, K. N.; Chang, S. M.; Fan, A.; Tan, C. S.; Shen, L. C.; Reif, R.
July 2005
Applied Physics Letters;7/18/2005, Vol. 87 Issue 3, p031909
Academic Journal
Process development of silicon layer stacking based on copper wafer bonding, grind-back, and etch-back was applied to demonstrate a strong four-layer-stack structure. Bonded copper layers in this structure became homogeneous layers and did not show original bonding interfaces. This process can be used in three-dimensional integrated circuit applications. Voids and total bonded area after each layer stacking were investigated for the bonding quality after each layer stacking. Large wafer bows from high residual stresses result in the structure failure at the stacking of a high number of layers.


Related Articles

  • Studies of chipping mechanisms for dicing silicon wafers. Luo, S. Y.; Wang, Z. W. // International Journal of Advanced Manufacturing Technology;Jan2008, Vol. 35 Issue 11/12, p1206 

    The purpose of this study was to investigate the chipping modes produced in the die edges of dicing silicon wafer using the thin diamond blades. The effects of dicing directions and different wafer types on the chipping size were studied. Furthermore, scratching tests were also used to assist...

  • Wafer.  // Network Dictionary;2007, p521 

    An encyclopedia entry for "Wafer" is presented. It is a piece of thin, round semiconductor material typically silicon which is used to make microchips. Silicon crystal which is grown into a large cylindrical ingot was sliced into very thin wafers.

  • Near Surface Photo-Voltage For Silicon Wafer Metrology. Tsidilkovski, Edward; Steeples, Kenneth // AIP Conference Proceedings;2005, Vol. 788 Issue 1, p589 

    High modulation frequency surface photo-voltage response, through non contact capacitance measurements on silicon wafers, up to 300mm diameter have been developed to provide a sensitive, repeatable quantification of doping density, crystal damage, and trace contamination. Real-time, non-contact...

  • Machining characteristics on the ultra-precision dicing of silicon wafer. Sung-Chul Kim; Eun-Sang Lee; Nam-Hun Kim; Hae-Do Jeong // International Journal of Advanced Manufacturing Technology;Jun2007, Vol. 33 Issue 7/8, p662 

    Recently, the slightest damage to a circuit can cause great damage due to the sizes of semiconductor chips becoming smaller. To prevent damage to the circuit, the dicing process for silicon wafer must be controlled. In this study, the relationship between the chipping effect and the force of...

  • Observation of silicon front surface topographs of an ultralarge-scale-integrated wafer by synchrotron x-ray plane wave. Suzuki, Yoshifumi; Tsukasaki, Yoshimitsu; Kajiwara, Kentaro; Kawado, Seiji; Iida, Satoshi; Chikaura, Yoshinori // Journal of Applied Physics;12/1/2004, Vol. 96 Issue 11, p6259 

    Surface roughness and undulation of unpatterned silicon wafers are serious issues for ultralarge-scale-integrated circuit devices, even after fine mechanochemical polishing. It has never been clarified whether the undulations exist only on the surface or also exist inside the bulk crystal. We...

  • Contactless optical evaluation of processing effects on carrier lifetime in silicon. Baude, P. F.; Tamagawa, T.; Polla, D. L. // Applied Physics Letters;12/10/1990, Vol. 57 Issue 24, p2579 

    Contactless, optical modulation of free-carrier absorption has been used to identify minority-carrier lifetime degradation associated with both novel and common very large scale integrated circuit processing steps in p-type silicon wafers. Carrier lifetime degradation and a corresponding...

  • No cooling-off period for annealing. Feng, LucĂ­a M. // Solid State Technology;Nov2004, Vol. 47 Issue 11, p80 

    Explains the applicability of anneal technology in device scaling. Cost-effectiveness of anneal technology in minimizing the transient-enhanced diffusion through the silicon device; Temperature required to activate the dopant and repair implant damage; Effects of ultrashort heating time on wafers.

  • Keeping data safe: Blow it up.  // R&D Magazine;Feb2002, Vol. 44 Issue 2, p13 

    Presents information on silicon wafers, a raw material for computer chips that can be turned into tiny explosives, according to chemists at the University of San Diego, California. Composition of the silicon wafers; Role of gadolinium and silicon-based explosives in the chemical analysis of...

  • SEMI SMG Reports Q2 Shipments.  // Advanced Packaging;Nov2003, Vol. 12 Issue 11, p12 

    Reports on the quarterly analysis of the silicon wafer industry conducted by SEMI Silicon Manufacturers Group (SMG) indicating that worldwide silicon wafer area shipments increased by eight percent during the second quarter of 2003 when compared to the first quarter. Background on SMG; Total...


Read the Article


Sorry, but this item is not currently available from your library.

Try another library?
Sign out of this library

Other Topics