TITLE

Fabrication and characterization of vertical-type, self-aligned asymmetric double-gate metal-oxide-semiconductor field-effect-transistors

AUTHOR(S)
Masahara, Meishoku; Liu, Yongxun; Ishii, Kenichi; Sakamoto, Kunihiro; Matsukawa, Takashi; Tanoue, Hisao; Kanemaru, Seigo; Suzuki, Eiichi
PUB. DATE
March 2005
SOURCE
Applied Physics Letters;3/21/2005, Vol. 86 Issue 12, p123512
SOURCE TYPE
Academic Journal
DOC. TYPE
Article
ABSTRACT
For gate work function engineering required for ultrathin channel (UTC) double-gate (DG) metal-oxide-semiconductor field-effect-transistor (MOSFET), threshold voltage (Vth) tuning of self-aligned asymmetric (n+–p+) DG MOSFETs have been experimentally investigated in comparison with symmetric (n+–n+) DG MOSFETs. The vertical UTCs (12–32 nm) were fabricated on bulk Si substrates by utilizing the novel ion-bombardment-retarded wet etching and the self-aligned asymmetric DGs were formed by employing the tilted ion implantation and anisotropic dry etching. The fabricated vertical asymmetric DG n-MOSFET with the gate length of 100 nm clearly exhibits the desirable Vth of +0.1 V, in addition to the unique DG MOSFET characteristics of the high short-channel-effect immunity with decreasing a channel thickness.
ACCESSION #
16581675

 

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