Abnormal enhancement of interface trap generation under dynamic oxide field stress at MHz region

Shiyang Zhu; Nakajima, Anri; Ohashi, Takuo; Miyake, Hideharu
February 2005
Applied Physics Letters;2/21/2005, Vol. 86 Issue 8, p083501
Academic Journal
By stressing metal-oxide-semiconductor field-effect transistors with ultrathin silicon dioxide or oxynitride gate dielectrics under square wave form voltage at the MHz region, an abnormal enhancement of interface trap generation in the midchannel region has been observed at some special frequencies. A hypothesis, including self-accelerating interface trap generation originated from the positive feedback of a charge pumping current to be contributed by the stress-induced near-interface oxide traps and a resonant tunneling via the near interface oxide trap states at those frequencies, is proposed to explain the observed phenomenon.


Related Articles

  • Effects of aging on the 1/f noise of metal-oxide-semiconductor field effect transistors. Zhou, X. J.; Fleetwood, D. M.; Danciu, I.; Dasgupta, A.; Francis, S. A.; Touboul, A. D. // Applied Physics Letters;10/22/2007, Vol. 91 Issue 17, p173501 

    The 1/f noise magnitude of n-channel metal-oxide-semiconductor field effect transistors is found to decrease by up a factor of ∼3 after 18 years of room-temperature aging. This decrease is largest in devices with high-temperature post-gate-oxidation N2 annealing, which increases the...

  • Effective mobilities in pseudomorphic Si/SiGe/Si p-channel metal-oxide-semiconductor field-effect transistors with thin silicon capping layers. Palmer, M. J.; Braithwaite, G.; Grasby, T. J.; Phillips, P. J.; Prest, M. J.; Parker, E. H. C.; Whall, T. E.; Parry, C. P.; Waite, A. M.; Evans, A. G. R.; Roy, S.; Watling, J. R.; Kaya, S.; Asenov, A. // Applied Physics Letters;3/5/2001, Vol. 78 Issue 10, p1424 

    The room-temperature effective mobilities of pseudomorphic Si/Si[sub 0.64]Ge[sub 0.36]/Si p-metal-oxidesemiconductor field effect transistors are reported. The peak mobility in the buried SiGe channel increases with silicon cap thickness. It is argued that SiO[sub 2]/Si interface roughness is a...

  • Process-induced positive charges in Hf-based gate stacks. Zhao, C. Z.; Zhang, J. F.; Chang, M. H.; Peaker, A. R.; Hall, S.; Groeseneken, G.; Pantisano, L.; De Gendt, S.; Heyns, M. // Journal of Applied Physics;Jan2008, Vol. 103 Issue 1, p014507 

    Hf-based gate stacks will replace SiON as a gate dielectric even though our understanding of them is incomplete. For an unoptimized SiO2 layer, an exposure to H2 at a temperature over 450 °C can lead to positive charging. In this work, we will show that a thermal exposure of Hf-based gate...

  • General framework about defect creation at the Si/SiO2 interface. Guerin, C.; Huard, V.; Bravaix, A. // Journal of Applied Physics;Jun2009, Vol. 105 Issue 11, p114513-1 

    This paper presents a theoretical framework about interface state creation rate from Si–H bonds at the Si/SiO2 interface. It includes three main ways of bond breaking. In the first case, the bond can be broken, thanks to the bond ground state rising with an electrical field. In two other...

  • Density of states of P[sub b1] Si/SiO[sub 2] interface trap centers. Campbell, J. P.; Lenahan, P. M. // Applied Physics Letters;3/18/2002, Vol. 80 Issue 11, p1945 

    The electronic properties of the (100) Si/SiO[sub 2] interfacial defect called P[sub b1] are quite controversial. We present electron spin resonance measurements that demonstrate: (1) that the P[sub b1] defects have levels in the silicon band gap, (2) that the P[sub b1] correlation energy is...

  • Relationship between channel mobility and interface state density in SiC metal–oxide–semiconductor field-effect transistor. Harada, Shinsuke; Kosugi, Ryoji; Senzaki, Junji; Cho, Won-Ju; Fukuda, Kenji; Arai, Kazuo; Suzuki, Seiji // Journal of Applied Physics;2/1/2002, Vol. 91 Issue 3, p1568 

    Temperature dependence of threshold voltage in n-channel SiC metal–oxide–semiconductor field-effect transistors (MOSFETs) was studied. Linear relation was observed between the threshold voltage shift when the temperature varies from -150 to 150 °C and the number of the interface...

  • Transport properties of single-crystal tetracene field-effect transistors with silicon dioxide gate dielectric. Newman, Christopher R.; Chesterfield, Reid J.; Merlo, Jeffrey A.; Frisbie, C. Daniel // Applied Physics Letters;7/19/2004, Vol. 85 Issue 3, p422 

    Single-crystal organic field-effect transistors (SX-OFETs) with channel lengths of 1 and 100 μm have been fabricated by adhering thin crystals of tetracene to freshly ashed SiO2 substrates containing countersunk gold contacts. The intrinsic transport properties of the tetracene single...

  • Figure of merit for and identification of sub-60 mV/decade devices. Vandenberghe, William G.; Verhulst, Anne S.; Sorée, Bart; Magnus, Wim; Groeseneken, Guido; Smets, Quentin; Heyns, Marc; Fischetti, Massimo V. // Applied Physics Letters;1/7/2013, Vol. 102 Issue 1, p013510 

    A figure of merit I60 is proposed for sub-60 mV/decade devices as the highest current where the input characteristics exhibit a transition from sub- to super-60 mV/decade behavior. For sub-60 mV/decade devices to be competitive with metal-oxide-semiconductor field-effect devices, I60 has to be...

  • Effects of high temperature forming gas anneal on the characteristics of metal-oxide-semiconductor field-effect transistor with HfO2 gate stack. Choi, Rino; Kang, Chang Seok; Cho, Hag-Ju; Kim, Young-Hee; Akbar, Mohammad S.; Lee, Jack C. // Applied Physics Letters;6/14/2004, Vol. 84 Issue 24, p4839 

    The effects of high temperature forming gas (N2:H2=96:4) anneal (600 °C) prior to metallization have been evaluated in terms of the improvement in the carrier mobility of HfO2/nitride layer gate stack metal-oxide-semiconductor field-effect transistors with TaN gate electrode. The...


Read the Article


Sorry, but this item is not currently available from your library.

Try another library?
Sign out of this library

Other Topics