TITLE

Voltage-induced degradation in self-aligned polycrystalline silicon gate n-type field-effect transistors with HfO2 gate dielectrics

AUTHOR(S)
Jaehoo Park; Moonju Cho; Hong Bae Park; Tae Joo Park; Suk Woo Lee; Sug Hun Hong; Doo Seok Jeong; Chihoon Lee; Cheol Seong Hwang
PUB. DATE
December 2004
SOURCE
Applied Physics Letters;12/13/2004, Vol. 85 Issue 24, p5965
SOURCE TYPE
Academic Journal
DOC. TYPE
Article
ABSTRACT
The voltage-induced degradation in the threshold voltage of field-effect transistors using atomic layer deposited HfO2-gate dielectrics was studied. Si channel surfaces of some samples were in situ pretreated using O3 flow before HfO2 deposition, which formed a very thin SiO2 interfacial layer. This avoided a shift of the threshold voltage up to a stress time of 1000 s under inversion condition at +3 V gate voltage. The transistors without O3 pretreatment showed a serious change in the threshold voltage by electron trapping. A leakage current measurement under inversion condition showed that the leakage current was not the major factor that controlled the degradation. Instead, the interfacial traps resulting from the Si suboxide formation for the cases without O3 pretreatment appeared to constitute the major reason for the degradation.
ACCESSION #
15331851

 

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