TITLE

Next Gen Switch/Router Design Issues

AUTHOR(S)
Stuck, Bart; Weingarten, Michael
PUB. DATE
October 2004
SOURCE
Business Communications Review;Oct2004, Vol. 34 Issue 10, p44
SOURCE TYPE
Trade Publication
DOC. TYPE
Article
ABSTRACT
This article presents a discussion by addressing the following questions: Why are current switch/router and port/line card designs unable to support the necessary speed and functionality? What are possible solutions? Replace/encapsulate the incoming packet header and apply an appropriate outgoing header, according to the parsing classification rules. Encapsulation examples include Intel's Advanced Switching and the IETF's Multiprotocol Label Switching. n the past, switch designers counted on only about 20 percent of packets requiring exceptional processing, so they designed control planes with only about 20 percent of the capacity of the data planes. Packets that required exceptional processing were described as traveling via the "slow path" through the control plane, while the rest took the "fast path" through the data plane. More recently, vendors such as Cisco, Foundry and Juniper have developed switch/routers that process all packets through the control plane. The switching interface is a Layer 2, dataplane function with minimal control plane activity. INSETS: Executive Summary;Decoding The Acronyms.
ACCESSION #
14728306

 

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