EDA aids power management in the design flow

Maheshwary, Rajiv
May 2004
Portable Design;May2004, Vol. 10 Issue 5, p24
Today, one in five integrated circuits designs fail in tape-out due to power-related issues. For this reason, power management is considered a necessary part of every original equipment manufacturing (OEM) and integrated circuit design flow. Also, there is a growing interest in the evolution of power management techniques to address the challenges faced by system and integrated circuits designers. The goal of power management is to ensure all applications and operations in the OEM end product are properly powered and that the product is reliable. This article reports that IC designers select Electronic Design Automation tools and flows for power management based on several criteria.


Related Articles

  • Wire-centric approaches ease IC development. Naum, Michael // Portable Design;May2004, Vol. 10 Issue 5, p26 

    To satisfy the market's insatiable appetite for denser, faster, and smaller products, portable-device integrated circuits designers must become power-versus-feature-aware. While cramming lots of functions into one chip makes marketing happy, it leaves logic designers to contend with headaches,...

  • Power vs. performance tradeoff may be a thing of the past. Master, Paul // Portable Design;May2004, Vol. 10 Issue 5, p28 

    Over the years, designers have been faced with the perennial power consumption versus performance deign tradeoff. In addition, designers must confront which integrated circuit technology will be the most appropriate and efficient for a given application. The design challenge is compounded by the...

  • Portable-system designers gain from structure. Gallagher, John // Portable Design;May2004, Vol. 10 Issue 5, p22 

    Designing an Application Specific Integrated Circuit (ASIC) into portable applications has many challenges above and beyond the usual gauntlet of ASIC design issues. Power dissipation; the ability to withstand environmental conditions like moisture, shock, and vibration; meeting short...

  • Divide and conquer complex chips designs. Rodman, Paul // EDN;7/8/2004, Vol. 49 Issue 14, p73 

    This article focuses on using a hierarchical-design approach for developing a complex chip. Historically, designers have used a hierarchical approach to chip design. Adopting a hierarchical approach has the advantage of enabling concurrent register-transfer-level and physical design because...

  • Tools take asynchronous design mainstream. Santarini, Michael // EDN Europe;Apr2006, Vol. 51 Issue 4, p18 

    The article features tools from Silistix that will free integrated circuit designers from slavery to a single system clock by allowing them to stitch together integrated circuit-design blocks with the use of asynchronous Internet protocol bus. The practical method for advanced designers is...

  • Back to Basics Part 20 - Design Features That Provide Tear Resistance. Fjelstad, Joe // CircuiTree;Sep2008, Vol. 21 Issue 9, p24 

    The article discusses the need for integrated circuit design features that provide tear resistance in flexible circuits. It enumerates several methods which include making sure all internal corners are provided with a generous radius, leaving tear stop metal in corners and using radiused slots....

  • Microcontroller delivers voltage-multiplied dc power. Lager, Aaron // EDN;5/11/2006, Vol. 51 Issue 10, p76 

    This article presents an integrated circuit (IC) design in which microcontroller provides voltage-multiplied direct current power. Sometimes the combination of an external circuit and a low-voltage microcontroller requires a higher power-supply voltage. For this applications, an external boost...

  • TRAFFIC MANAGEMENT: A GROWING NIGHTMARE FOR SOC DESIGNERS. Wilson, Ron // EDN;11/8/2007, Vol. 52 Issue 23, p48 

    The article addresses the changes in the interconnect architecture of system on chip (SOC). There are increasing indications that the centralized-bus approach to SOC interconnect is simply becoming unpopular. As the number of processing nodes on an integrated circuit increases and as the data...

  • Increasing abstraction makes DFT more effective.  // EDN Europe;Jan2008, Vol. 53 Issue 1, p18 

    The article presents the author's views regarding the usefulness of design-for-test (DFT) functionality in testing the integrated circuits. The author states that chip quality is compromised in new deep submicron technologies because new defect types appear all the time. He adds that novel DFT...


Read the Article


Sorry, but this item is not currently available from your library.

Try another library?
Sign out of this library

Other Topics