65-nm semiconductor process to be sampled in 2005

May 2004
Portable Design;May2004, Vol. 10 Issue 5, p8
A newly-developed 65 nanometer (nm) semiconductor manufacturing-process technology is expected to shrink equivalent 90-nm designs by half and boost transistor performance 40 percent. The new technology can also reduce leakage power from idle transistors while simultaneously integrating hundreds of millions of transistors that support both analog and digital functions in system-on-chip configurations, The developer, Texas Instruments, has 4-Mbit SRAM memory test arrays functional today and plans to sample a wireless product built with the new process in the first quarter of 2005.


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