Extension of Coulomb blockade region by quantum confinement in the ultrasmall silicon dot in a single-hole transistor at room temperature

Saitoh, Masumi; Hiramoto, Toshiro
April 2004
Applied Physics Letters;4/19/2004, Vol. 84 Issue 16, p3172
Academic Journal
First room-temperature (RT) observation of extended Coulomb blockade (CB) region due to quantum confinement in the ultrasmall silicon dot in a single-hole transistor (SHT) is described. We fabricate single-dot SHTs in the form of metal-oxide-semiconductor field-effect transistors with an extremely constricted channel. Both large CB oscillation with the peak-to-valley current ratio (PVCR) of 40.4 and clear negative differential conductance (NDC) with the PVCR of 11.8 (highest ever reported) are observed at RT in the fabricated device. The observed NDC is attributable to the resonant tunneling due to the large quantum level spacing in the ultrasmall dot whose size is estimated to be about 2 nm. © 2004 American Institute of Physics.


Related Articles

  • Double-polysilicon self-aligned lateral bipolar transistors. Pengpad, P.; Bagnall, D. M. // Journal of Materials Science: Materials in Electronics;Feb2008, Vol. 19 Issue 2, p183 

    A new lateral bipolar junction transistor that utilises a double-polysilicon self-aligned structure to maximise high-frequency performance is introduced. Silicon-on-oxide (SOI) wafers are used to isolate devices from the substrate and to minimise parasitic substrate capacitances (CJCS0) around...

  • Coulomb oscillations based on band-to-band tunneling in a degenerately doped silicon metal-oxide-semiconductor field-effect transistor. Kyung Rok Kim; Dae Hwan Kim; Jong Duk Lee; Byung-Gook Park // Applied Physics Letters;4/19/2004, Vol. 84 Issue 16, p3178 

    We report Coulomb oscillations based on band-to-band tunneling through a valence band in silicon metal-oxide-semiconductor field-effect transistors. Degenerately p+-doped channel and n+-doped source/drain enables band-to-band tunneling, which can play a major role in the transport between the...

  • Low-temperature conductance oscillations in junctionless nanowire transistors. Park, Jong-Tae; Kim, Jin Young; Lee, Chi-Woo; Colinge, Jean-Pierre // Applied Physics Letters;10/25/2010, Vol. 97 Issue 17, p172101 

    Junctionless nanowire transistors show more marked oscillations conductance oscillations than inversion-mode devices. These oscillations can be observed at higher temperature, drain voltage, and gate voltage than in surface-channel, inversion-mode multigate metal-oxide-semiconductor field-effect...

  • Packages Have Become the New ICs. Colvin, Jim // Electronic Device Failure Analysis;Nov2014, Vol. 16 Issue 4, p2 

    The article presents brief information on n-channel Metal oxide semiconductor field-effect transistors (MOSFET) NMOS and Complementary metal?oxide?semiconductor (CMOS). It mentions how curvature of the package increases during thinning, leaving the center region thinner than the edge, with the...

  • Thermal Noise Analysis of a Double Gate MOSFET Using Si and GaAs Substrate with Various Oxide Layers. Panda, Saradindu; Dash, Suryadeepta; Maji, Bansibadan; Mukhopadhyay, Asish Kumar // International Journal of Research & Reviews in Computer Science;Jun2012, Vol. 3 Issue 3, p1616 

    The most promising VLSI devices in the nano range are based on multiple gate structures such as double- gate (DG) MOSFETs. These devices can be used in high frequency applications due to their high transition frequency (fT), This can therefore be significant in noise models required for low...

  • Low-Frequency Noise Behavior at Low Temperature (80K–300K) of Silicon Passivated Ge pMOSFETs with High-K Metal Gate Stack. Guo, W.; Cretu, B.; Routoure, J.-M.; Carin, R.; Mercha, A.; Simoen, E.; Claeys, C. // AIP Conference Proceedings;2007, Vol. 922 Issue 1, p29 

    The low frequency noise performance of pMOSFETs with high-K and metal gate on epitaxial Germanium (Ge) on silicon (Si) substrates from 300K down to 80K has been investigated. The gate stack consists of a TiN/TaN metal gate on top of a 1.3nm EOTHfO2-SiO2 gate dielectric bi-layer. A typical...

  • Impact of hot carrier degradation and positive bias temperature stress on lateral 4H-SiC nMOSFETs. Pobegen, Gregor; Aichinger, Thomas; Salinaro, Alberto; Grasser, Tibor // Materials Science Forum;2014, Vol. 778-780, p959 

    We study the impact of positive bias temperature stress (PBTS) and hot carrier stress (HCS) on lateral 4H-SiC nMOSFETs. These degradation mechanisms are prominent in silicon (Si) based devices where both create oxide (OT) as well as interface traps (IT) [1, 2]. For SiC MOSFETs only limited...

  • A Simulation Model for the H-gate PDSOI MOSFET. Bu Jianhui; Bi Jinshun; Liu Mengxin; Luo Jiajun; Han Zhengsheng // World Academy of Science, Engineering & Technology;2012, Issue 71, p1413 

    The floating body effect is a serious problem for the PDSOI MOSFET, and the H-gate layout is frequently used as the body contact to eliminate this effect. Unfortunately, most of the standard commercial SOI MOSFET model is for the device with finger gate, the necessity of the new models for the...

  • Observation of nonstationary transport in deep submicron n-channel metal-oxide-semiconductor transistors with Shubnikov–de Haas oscillations. Miéville, Jean-Paul; Ouisse, Thierry; Cristoloveanu, Sorin; Forro, Lazlo; Revil, Nathalie; Dutoit, Michel // Journal of Applied Physics;4/15/1994, Vol. 75 Issue 8, p4226 

    Presents information on a study which investigated the effect of the lateral electric field on the amplitude of Shubnikov-de Haas oscillations in silicon metal-oxide-semiconductor field-effect transistors. Analysis of Shubnikov-de Haas oscillations; Methodology of the study; Results and discussion.


Read the Article


Sorry, but this item is not currently available from your library.

Try another library?
Sign out of this library

Other Topics