Things to come
- Moore's Law challenges European semi players. Rossman, Franz Joachim // EDN;11/11/2004 Supplement2, Vol. 49, p56
This article looks at the performance of the European semiconductor industry. Few European integrated circuit (IC) companies have the financial and technical resources to handle the demands of Moore's Law. But a few multinational vendors do quite well, and partnerships will keep these vendors...
- Untitled. Double, Paul // Electronics Weekly;7/19/2006, Issue 2250, p22
The article reports that ASIC design and production has got cheaper for many projects over the last ten years. Cheaper ASIC design is due to choosing the appropriate fabrication process and selecting cost-effective EDA tools. Design costs for older processes have also fallen, particularly for...
- Slack EDA-market growth doesn't portend chip trends. Wright, Maury // EDN;3/16/2006, Vol. 51 Issue 6, p14
The article focuses on a DesignCon panel that set out to discuss stagnant electronic design automation (EDA) growth which ended up pointing out just how big the separation between EDA and the semiconductor industry can be. Panelists made statements about the chip business that both help explain...
- Successful IC Design Takes Front--And Back--End Teamwork. Gallagher, John // Electronic Design;4/1/2002, Vol. 50 Issue 7, p44
Presents guidelines for the successful design of advanced integrated circuits (IC). Front- and back-end design; Barriers to achieve a more connected design flow; Design of application specific IC.
- FAST-TURNAROUND ASIC PLATFORMS SPEED COMPLEX CHIPS TO MARKET. Bursky, Dave // Electronic Design;2/17/2003, Vol. 51 Issue 4, p40
Focuses on the advances in application specific integrated circuits (ASIC) design. Reduction of design time from concept to final functional silicon; Reference to a fast-turnaround design platform for ASIC; Use of predesigned blocks.
- Design options are confusing low end Asics customers. // Electronics Weekly;10/2/2002, Issue 2070, p14
Comments on the availability of middle-ground applications specific integrated circuits (Asics) which offers a number of design choices for chips. Companies that offer middle-ground Asics; Effect of the middle-ground Asics on customers of electronics industries.
- Deep-submicron designs will not converge without IC floorplanning. Kompolt, Steve // Electronic Design;4/3/95, Vol. 43 Issue 7, p59
Focuses on the convergence of deep-submicron design technology using floorplanning. Integrated circuit design; Interconnect and gate-level models; Nature of synthesis; Dominance of interconnect delay; Move to higher clock speeds; Timing constraints; RTL estimation.
- Delay calculation methods need to change for deep-submicron ICs. Wiederhold, Bob // Electronic Design;4/3/95, Vol. 43 Issue 7, p60
Focuses on the need to evaluate strategies for deep-submicron delay calculations. Design's speed objectives; Design cycle; Intelligent extraction; Delay-correlation problems; Slope dependence; Nonlinear drive strength.
- Speeding time-to-market demands: a new approach to design closure. Groeneveld, Patrick; Desmarais, Dick // EDN;07/06/2000, Vol. 45 Issue 14, p85
Examines an approach to design closure to speed time-to-market demands for application specific integrated circuits. Evaluation of design flow, methodologies and design tools; Prediction of interconnect delays; Ways for addressing submicron-process technology.