TITLE

233-비트 이진체 타원곡선을 지원하는 암호 프로세서의 저면적 구현

AUTHOR(S)
박병관; 신경욱
PUB. DATE
July 2017
SOURCE
Journal of the Korea Institute of Information & Communication En;Jul2017, Vol. 21 Issue 7, p1267
SOURCE TYPE
Academic Journal
DOC. TYPE
Article
ABSTRACT
This paper describes a design of cryptographic processor supporting 233-bit elliptic curves over binary field defined by NIST. Scalar point multiplication that is core arithmetic in elliptic curve cryptography(ECC) was implemented by adopting modified Montgomery ladder algorithm, making it robust against simple power analysis attack. Point addition and point doubling operations on elliptic curve were implemented by finite field multiplication, squaring, and division operations over GF(2233), which is based on affine coordinates. Finite field multiplier and divider were implemented by applying shift-and-add algorithm and extended Euclidean algorithm, respectively, resulting in reduced gate counts. The ECC processor was verified by FPGA implementation using Virtex5 device. The ECC processor synthesized using a 0.18 um CMOS cell library occupies 49,271 gate equivalents (GEs), and the estimated maximum clock frequency is 345 MHz. One scalar point multiplication takes 490,699 clock cycles, and the computation time is 1.4 msec at the maximum clock frequency.
ACCESSION #
125498829

 

Related Articles

  • Enforced Conviction in Cryptographic Provenance Across Critical System Information. Prince Asha N. // International Journal of Computer Science & Information Technolo;2014, Vol. 5 Issue 3, p3491 

    This project's aim is to describe two application, first one is keystroke integrity verification and secondly, malicious traffic detection or traffic monitoring. In this project we design and implement a cryptographic protocol that impose keystroke integrity by utilizing trusted computing...

  • Implementation of AES as a Reconfigurable Cryptographic Embedded system using MicroBlaze & Xilinx ISE. Jaiswal, M. P.; Sarate, G. G.; Hirekhan, S. R. // International Journal of Computer Science Engineering & Technolo;Mar2011, Vol. 1 Issue 2, p77 

    In this paper implementation of AES as a reconfigurable cryptographic embedded system is described. With some proposed techniques, an optimized structure of AES is discussed. The implementations of AES are described as a reconfigurable hardware approach of embedded system using MicroBlaze SCP. A...

  • Design of an Efficient Hybrid Crypto-Processor. Jianzhou Li; Hua Li; Wei Dong // International Journal for Computers & Their Applications;Dec2012, Vol. 19 Issue 4, p232 

    In this paper, an efficient hybrid crypto-processor design has been proposed. In our proposed processor architecture, a multiplier over Galois Field (GF) has been presented to support public-key cryptographic algorithms and the symmetric-key cryptographic algorithms over GF(p) and GF(2n) such as...

  • On the choice of the appropriate AES data encryption method for ZigBee nodes. Ottoy, G.; Hamelinckx, T.; Preneel, B.; De Strycker, L.; Goemaere, J.-P. // Security & Communication Networks;1/25/2016, Vol. 9 Issue 2, p87 

    This paper describes the experiments that have been conducted to determine the optimal implementation method for AES (Advanced Encryption Standard) data encryption in a ZigBee network in terms of energy consumption. Four possible scenarios have been considered. The first one is a freely...

  • IBM switches on Crypto adapter. Gruener, James // PC Week;08/04/97, Vol. 14 Issue 33, p27 

    Describes the purpose of IBM's new 4758 PCI Cryptographic Co-processor/Adapter. The ability of the cryptographic device to encrypt data as it passes to the Internet; The goal of streamlining E-commerce transactions; Other features.

  • Design and implementation of a versatile cryptographic unit for RISC processors. Yumbul, Kazim; Savaş, Erkay; Kocabaş, Övünç; Großschädl, Johann // Security & Communication Networks;Jan2014, Vol. 7 Issue 1, p36 

    ABSTRACT In this paper, we design, implement, and realize a cryptographic unit (CU) that can easily be integrated to any reduced instruction set computing (RISC)-type processor for the safe and efficient execution of cryptographic algorithms. Design of the CU takes a novel approach in the...

  • Flexible Architectures for Cryptographic Algorithms — A Systematic Literature Review. Rashid, Muhammad; Imran, Malik; Jafri, Atif Raza; Al-Somani, Turki F. // Journal of Circuits, Systems & Computers;Mar2019, Vol. 28 Issue 3, pN.PAG 

    Symmetric and asymmetric cryptographic algorithms are used for a secure transmission of data over an unsecured public channel. In order to use these algorithms in real-time applications, many flexible hardware architectures have been proposed and implemented with multiple design constraints....

  • A New Approach on Discrete Chaotic Cryptography Using TMS320C6713 Digital Signal Processors. Saravanan, R.; Sivaramakrishnan, T. R.; Ramamoorthy, K. // International Journal of Applied Engineering Research;2007, Vol. 2 Issue 3, p545 

    This paper presents an algorithm for secure transmission of message by combining chaotic systems with stream ciphers for digital communication. To develop this chaotic cryptographic algorithm, one of the simplest discrete chaotic maps called Henon map has been used. A Texas Instrument's floating...

  • Self-Partial and Dynamic Reconfiguration Implementation for AES using FPGA. Ismaili, Zine El Abidine Alaoui; Moussa, Ahmed // International Journal of Computer Science Issues (IJCSI);Jul2010, Vol. 7 Issue 4, p33 

    This paper addresses efficient hardware/software implementation approaches for the AES (Advanced Encryption Standard) algorithm and describes the design and performance testing algorithm for embedded system. Also, with the spread of reconfigurable hardware such as FPGAs (Field Programmable Gate...

  • Enhancing a 32-Bit Processor Core with Efficient Cryptographic Instructions. Benhadjyoussef, Noura; Elhadjyoussef, Wajih; Machhout, Mohsen; Tourki, Rached; Torki, Kholdoun // Journal of Circuits, Systems & Computers;Dec2015, Vol. 24 Issue 10, p-1 

    Embedded processor is often expected to achieve a higher security with good performance and economical use of resource. However, the choice regarding the best solution for how cryptographic algorithms are incorporated in processor core is one of the most challenging assignments a designer has to...

Share

Read the Article

Courtesy of THE LIBRARY OF VIRGINIA

Sorry, but this item is not currently available from your library.

Try another library?
Sign out of this library

Other Topics