TITLE

A Jitter Suppressed DLL-Based Clock Generator

AUTHOR(S)
Young-Shig Choi; Gi-Yeong Ko
PUB. DATE
July 2017
SOURCE
Journal of the Korea Institute of Information & Communication En;Jul2017, Vol. 21 Issue 7, p1261
SOURCE TYPE
Academic Journal
DOC. TYPE
Article
ABSTRACT
A random and systematic jitter suppressed delay locked loop (DLL)-based clock generator with a delay-time voltage variance converter (DVVC) and an averaging circuit (AC) is presented. The DVVC senses the delay variance of each delay stage and generates a voltage. The AC averages the output voltages of two consecutive DVVCs to suppress the systematic and random delay variance of each delay stage in the VCDL. The DVVC and AC averages the delay time of successive delay stages and equalizes the delay time of all delay stages. In addition, a capacitor with a switch working effectively as a negative feedback function is introduced to reduce the variation of the loop filter output voltage. Measurement results of the DLL-based clock generator fabricated in a one-poly six-metal 0.18μm CMOS process shows 13.4-ps rms jitter.
ACCESSION #
125498828

 

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