Lateral interband tunneling transistor in silicon-on-insulator

Aydin, C.; Zaslavsky, A.; Luryi, S.; Cristoloveanu, S.; Mariolle, D.; Fraboulet, D.; Deleonibus, S.
March 2004
Applied Physics Letters;3/8/2004, Vol. 84 Issue 10, p1780
Academic Journal
We report on a lateral interband tunneling transistor, where the source and drain form a heavily doped lateral pn junction in a thin Si film on a silicon-on-insulator (SOI) substrate. The transistor action results from the control of the reverse-bias tunneling breakdown under drain bias V[sub D] by a gate voltage V[sub G]. We observe gate control over tunneling drain current I[sub D] at both polarities of V[sub G] with negligible gate leakage. Systematic I[sub D](V[sub G],V[sub D]) measurements, together with numerical device simulations, show that in first approximation I[sub D] depends on the maximum junction electric field F[sub max](V[sub G],V[sub D]). Excellent performance is hence predicted in devices with more abrupt junctions and thinner SOI films. The device does not have an inversion channel and is not subject to scaling rules of standard Si transistors. © 2004 American Institute of Physics.


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