TITLE

Simulations of threshold voltage instabilities in Hf[sub y]SiO[sub x] and SiO[sub 2]/Hf[sub y]SiO[sub x]-based field-effect transistors

AUTHOR(S)
Houssa, M.; Bizzari, C.; Autran, J.L.
PUB. DATE
December 2003
SOURCE
Applied Physics Letters;12/15/2003, Vol. 83 Issue 24, p5065
SOURCE TYPE
Academic Journal
DOC. TYPE
Article
ABSTRACT
Threshold voltage shifts in metal-oxide-semiconductor field-effect transistors with Hf[sub y]SiO[sub x] gate layers and SiO[sub 2]/Hf[sub y]SiO[sub x] gate stacks have been simulated, taking into account the generation of Si trivalent dangling bonds at the Si/dielectric interface, resulting from the injection of electrons through the structure. While the tunneling current flowing through devices with Hf[sub y]SiO[sub x] single layers is predicted to be lower compared to devices with SiO[sub 2]/Hf[sub y]SiO[sub x] gate stacks (with equivalent electrical thickness), it is found that the transistor lifetime, based on threshold voltage shifts, is improved in SiO[sub 2]/Hf[sub y]SiO[sub x] gate stacks. This finding is attributed to the beneficial presence of the SiO[sub 2] interfacial layer, which allows the relaxation of strain at the Si/dielectric interface. © 2003 American Institute of Physics.
ACCESSION #
11649636

 

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