TITLE

Characteristics of SiO[sub 2]/n-GaN interfaces with β-Ga[sub 2]O[sub 3] interlayers

AUTHOR(S)
Nakano, Yoshitaka; Kachi, Tetsu; Jimbo, Takashi
PUB. DATE
November 2003
SOURCE
Applied Physics Letters;11/24/2003, Vol. 83 Issue 21, p4336
SOURCE TYPE
Academic Journal
DOC. TYPE
Article
ABSTRACT
We report on the characteristics of SiO[sub 2]/n-GaN metal-oxide-semiconductor (MOS) structures with β-Ga[sub 2]O[sub 3] interlayers. β-Ga[sub 2]O[sub 3] 15 nm thick was grown by dry oxidation at 800 °C for 6 h, and 100-nm-thick SiO[sub 2] was then deposited by sputtering. Capacitance–voltage measurements show a low interface trap density of ∼3.9×10[sup 10] eV[sup -1] cm[sup -2], probably indicating an unpinning of the surface Fermi level. Additionally, current–voltage measurements display a low leakage current of ∼1.2 μA/cm2 at a gate voltage of +20 V, regardless of rough oxide surface, as confirmed by atomic force microscopy observations. Thus, the stacked SiO[sub 2]/β-Ga[sub 2]O[sub 3] insulator is found to improve both the electrical interface properties and the gate dielectric characteristics of the GaN MOS structures. © 2003 American Institute of Physics.
ACCESSION #
11447620

 

Related Articles

  • Study on Zr-silicate interfacial layer of ZrO[sub 2] metal-insulator-semiconductor structure. Yamaguchi, Takeshi; Satake, Hideki; Fukushima, Noburu; Toriumi, Akira // Applied Physics Letters;3/18/2002, Vol. 80 Issue 11, p1987 

    We have investigated the physical and dielectric properties of the Zr-silicate interfacial layer of ZrO[sub 2] metal-insulator-semiconductor (MIS) structure fabricated by pulsed-laser ablation deposition. It was found that an ultrathin Zr-silicate interfacial layer is formed on a Si substrate as...

  • Microscopic model for enhanced dielectric constants in low concentration SiO[sub 2]-rich noncrystalline Zr and Hf silicate alloys. Lucovsky, G.; Rayner, G. B.; Rayner Jr., G.B. // Applied Physics Letters;10/30/2000, Vol. 77 Issue 18 

    Dielectric constants, k, of Zr(Hf) silicate alloy gate dielectrics obtained from analysis of capacitance-voltage curves of metal-oxide-semiconductor capacitors with 3-6 at. % Zr(Hf) are significantly larger than estimates of k based on linear extrapolations between SiO[sub 2] and compound...

  • Constant voltage stress induced degradation in HfO[sub 2]/SiO[sub 2] gate dielectric stacks. Xu, Zhen; Houssa, Michel; Carter, Richard; Naili, Mohamed; De Gendt, Stefan; Heyns, Marc // Journal of Applied Physics;6/15/2002, Vol. 91 Issue 12, p10127 

    Defect generation in HfO[sub 2]/SiO[sub 2] gate dielectric stacks under constant voltage stress is investigated. It is found that the stress induced electrical degradation in HfO[sub 2]/SiO[sub 2] stacks is different than in the SiO[sub 2] layer. The variation of the gate leakage current with...

  • Metal-dielectric band alignment and its implications for metal gate complementary metal-oxide-semiconductor technology. Yeo, Yee-Chia; King, Tsu-Jae; Hu, Chenming // Journal of Applied Physics;12/15/2002, Vol. 92 Issue 12, p7266 

    The dependence of the metal gate work function on the underlying gate dielectric in advanced metal-oxide-semiconductor (MOS) gate stacks was explored. Metal work functions on high-κ dielectrics are observed to differ appreciably from their values on SiO[sub 2] or in vacuum. We applied the...

  • Trap-assisted tunneling in high permittivity gate dielectric stacks. Houssa, M.; Tuominen, M. // Journal of Applied Physics;6/15/2000, Vol. 87 Issue 12, p8615 

    Presents information on a study which investigated the electric properties of metal oxide semiconductor capacitors with thin SiO.../ZrO... and SiO.../Ta...O... gate dielectric stacks. Estimation of trap level energies and trap densities; Capacitance and voltage characteristics of the stacks;...

  • Model for the charge trapping in high permittivity gate dielectric stacks. Houssa, M.; Naili, M.; Heyns, M. M.; Stesmans, A. // Journal of Applied Physics;1/1/2001, Vol. 89 Issue 1, p792 

    The generation of traps in SiO[sub x]/ZrO[sub 2] and SiO[sub x]/TiO[sub 2] gate dielectric stacks during gate voltage stress of metal-oxide-semiconductor capacitors is investigated. The voltage and temperature dependence of the trap generation rate is extracted from the analysis of the gate...

  • Adhesion of metals and semiconductors analyzed by a dielectric formalism. Vakilov, A. N.; Mamonova, M. V.; Prudnikov, V. V. // Physics of the Solid State;Jun97, Vol. 39 Issue 6, p864 

    This paper discusses a model of the adhesive interaction of metals and semiconductors, based on a dielectric formalism and using the concepts of collective excitations — plasmons of the electron-ion system. Expressions are obtained in terms of the jellium model in the longwavelength...

  • Electrical and physical characteristics of PrTi[sub x]O[sub y] for metal-oxide-semiconductor gate dielectric applications. Jeon, Sanghun; Hwang, Hyunsang // Applied Physics Letters;12/16/2002, Vol. 81 Issue 25, p4856 

    The electrical and physical characteristics of PrTi[sub x]O[sub y], for use in metal-oxide-semiconductor gate dielectric applications were investigated. An amorphous layer of PrTi[sub x]O[sub y] with an equivalent oxide thickness of 1 nm and a dielectric constant of 23 was formed by means of...

  • A highly sensitive evaluation method for the determination of different current conduction mechanisms through dielectric layers. Murakami, Katsuhisa; Rommel, Mathias; Yanev, Vasil; Erlbacher, Tobias; Bauer, Anton J.; Frey, Lothar // Journal of Applied Physics;Sep2011, Vol. 110 Issue 5, p054104 

    Current conduction mechanisms through a metal-oxide semiconductor capacitor with a 9.6 nm thick SiO2 dielectric layer are characterized via Fowler-Nordheim (FN) and Poole-Frenkel (PF) plots, as well as through the analysis of the power exponent parameter α = d(log I)/d(log V). It is shown...

Share

Read the Article

Courtesy of

Sorry, but this item is not currently available from your library.

Try another library?
Sign out of this library

Other Topics