TITLE

Pillar-lattice-assisted stress-free silicon-on-insulator

AUTHOR(S)
Haisma, Jan
PUB. DATE
October 2003
SOURCE
Applied Physics Letters;10/20/2003, Vol. 83 Issue 16, p3323
SOURCE TYPE
Academic Journal
DOC. TYPE
Article
ABSTRACT
Standard silicon-on-insulator (SOI) technology is hampered by dilatation mismatch between silicon and its thermal oxide: the thin silicon top-layer is subjected to tensile stress. However, by combining three advanced technologies: covalent bonding, nanoimprint lithography, and Smart-Cut thinning, an insulating, pillar-lattice-structured, and bonded intermediate layer can be created to relieve the dilatation-determined tensile stress. The insulated silicon top-layer properties of this so-called lattice-SOI resemble those of bulk silicon. The layer optimizes the electrical characteristics, shows no warp, no stress-corrosion, and can be upgraded to a zero defect density by annealing. This proposal of lattice-SOI technology should have an important impact on the SOI quality level against bulk silicon in comparison with standard SOI. © 2003 American Institute of Physics.
ACCESSION #
11097792

 

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